Datasheet

©2011 Silicon Storage Technology, Inc. DS-25015A 04/11
13
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
Data Sheet
A
Microchip Technology Company
If a Program or Erase operation is attempted on a protected sector or block, the operation will abort.
After the device initiates an abort, the corresponding Write Operation Status Detection Bits will stay
active for approximately 200ns (program or erase) before the device returns to read mode.
For the status of these bits during a Write operation, see Table 4.
Data# Polling (DQ
7
)
When the SST38VF6401/6402/6403/6404 are in an internal Program operation, any attempt to read
DQ
7
will produce the complement of true data. For a Program Buffer-to-Flash operation, DQ7 is the
complement of the last word loaded in the Write-Buffer using the Write-to-Buffer command. Once the
Program operation is completed, DQ
7
will produce valid data. Note that even though DQ
7
may have valid
data immediately following the completion of an internal Write operation, the remaining data outputs may still be
invalid. Valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1
µs.
During an internal Erase operation, any attempt to read DQ
7
will produce a ‘0’. Once the internal Erase
operation is completed, DQ
7
will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is
valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 11 for Data# Polling timing diagram
and Figure 26 for a flowchart.
Toggle Bits (DQ
6
and DQ
2
)
During the internal Program or Erase operation, any consecutive attempts to read DQ
6
will produce
alternating ‘1’s and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the internal Program or Erase opera-
tion is completed, the DQ
6
bit will stop toggling, and the device is then ready for the next operation. For
Sector-, Block-, or Chip-Erase, the toggle bit (DQ
6
) is valid after the rising edge of sixth WE# (or CE#)
pulse. DQ
6
will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector or Block.
If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ
6
will toggle.
An additional Toggle Bit is available on DQ
2
, which can be used in conjunction with DQ
6
to check
whether a particular sector or block is being actively erased or erase-suspended. Table 4 shows
detailed bit status information. The Toggle Bit (DQ
2
) is valid after the rising edge of the last WE# (or
CE#) pulse of Write operation. See Figure 12 for Toggle Bit timing diagram and Figure 26 for a flow-
chart.
DQ
1
If an operation aborts during a Write-to-Buffer or Program Buffer-to-Flash operation, DQ
1
is set to ‘1’.
To reset DQ
1
to ‘0’, issue the Write-to-Buffer Abort Reset command to exit the abort state. A power-off/
power-on cycle or a Hardware Reset (RST# = 0) will also clear DQ
1
.