Datasheet

 2015 Microchip Technology Inc. DS20005119G-page 5
SST26VF064B / SST26VF064BA
FIGURE 2-4: PIN DESCRIPTION FOR 24-BALL TBGA
TABLE 2-1: PIN DESCRIPTION
Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SIO[3:0] Serial Data
Input/Output
To transfer commands, addresses, or data serially into the device or data out of
the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)
command instruction configures these pins for Quad I/O mode.
SI Serial Data Input
for SPI mode
To transfer commands, addresses or data serially into the device. Inputs are
latched on the rising edge of the serial clock. SI is the default state after a power
on reset.
SO Serial Data Output
for SPI mode
To transfer data serially out of the device. Data is shifted out on the falling edge
of the serial clock. SO is the default state after a power on reset.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence; or in the case of Write operations,
for the command/data input sequence.
WP# Write Protect The WP# is used in conjunction with the WPEN and IOC bits in the Configura-
tion register to prohibit write operations to the Block-Protection register. This pin
only works in SPI, single-bit and dual-bit Read mode.
HOLD# Hold Temporarily stops serial communication with the SPI Flash memory while the
device is selected. This pin only works in SPI, single-bit and dual-bit Read mode
and must be tied high when not in use.
V
DD
Power Supply To provide power supply voltage.
V
SS
Ground
NC
NC
NC
NC
NC
SCK
V
SS
V
DD
NC
CE#
NC
WP#/
SIO2
NC
S0/
SIO1
SI/
SIO0
HOLD#/
SIO3
NC
NC
NC
NC
NC
NC
NC
NC
ABCDE
F
1
2
3
4
T4D-P1.0
Top View