Datasheet

2015 Microchip Technology Inc. DS20005119G-page 33
SST26VF064B / SST26VF064BA
5.31 Write-Enable (WREN)
The Write Enable (WREN) instruction sets the Write-
Enable-Latch bit in the Status register to ‘1,’ allowing
Write operations to occur. The WREN instruction must
be executed prior to any of the following operations:
Sector Erase, Block Erase, Chip Erase, Page Program,
Program Security ID, Lockout Security ID, Write Block-
Protection Register, Lock-Down Block-Protection Reg-
ister, Non-Volatile Write-Lock Lock-Down Register, SPI
Quad Page program, and Write-Status Register. To
execute a Write Enable the host drives CE# low then
sends the Write Enable command cycle (06H) then
drives CE# high. See Figures 5-32 and 5-33 for the
WREN instruction sequence.
FIGURE 5-32: WRITE-ENABLE SEQUENCE (SQI)
FIGURE 5-33: WRITE-ENABLE SEQUENCE (SPI)
25119 F12.1
MODE 3 0 1
SCK
SIO[3:0]
CE#
06
MODE 0
CE#
SO
SI
SCK
01234567
06
HIGH IMPEDANCE
MODE 0
MODE 3
25119 F18.0
MSB