Datasheet
2015 Microchip Technology Inc. DS20005119G-page 27
SST26VF064B / SST26VF064BA
5.19 Chip-Erase
The Chip-Erase instruction clears all bits in the device
to ‘1.’ The Chip-Erase instruction is ignored if any of the
memory area is protected. Prior to any write operation,
execute the WREN instruction.
To execute a Chip-Erase operation, the host drives
CE# low, sends the Chip-Erase command cycle (C7H),
then drives CE# high. Poll the BUSY bit in the Status
register, or wait T
SCE,
for the completion of the internal,
self-timed, Write operation. See Figures 5-23 and 5-24
for the Chip Erase sequence.
FIGURE 5-23: CHIP-ERASE SEQUENCE (SQI)
FIGURE 5-24: CHIP-ERASE SEQUENCE (SPI)
25119 F09.1
MODE 3 0 1
SCK
SIO(3:0)
CE#
C1
C0
MODE 0
Note: C[1:0] = C7H
CE#
SO
SI
SCK
01234567
C7
HIGH IMPEDANCE
MODE 0
MODE 3
25119 F59.0
MSB