Datasheet

SST26VF064B / SST26VF064BA
DS20005119G-page 26  2015 Microchip Technology Inc.
5.18 Block-Erase
The Block-Erase instruction clears all bits in the
selected block to ‘1’. Block sizes can be 8 KByte, 32
KByte or 64 KByte depending on address, see Figure
3-1, Memory Map, for details. A Block-Erase instruction
applied to a protected memory area will be ignored.
Prior to any write operation, execute the WREN instruc-
tion. Keep CE# active low for the duration of any com-
mand sequence.
To execute a Block-Erase operation, the host drives
CE# low then sends the Block-Erase command cycle
(D8H), three address cycles, then drives CE# high.
Address bits A
MS
-A
13
determine the block address
(BA
X
); the remaining address bits can be V
IL
or V
IH
. For
32 KByte blocks, A
14
:A
13
can be V
IL
or V
IH
; for 64
KByte blocks, A
15
:A
13
can be V
IL
or V
IH
. Poll the BUSY
bit in the Status register, or wait T
BE,
for the completion
of the internal, self-timed, Block-Erase operation. See
Figures 5-21 and 5-22 for the Block-Erase sequence.
FIGURE 5-21: BLOCK-ERASE SEQUENCE (SQI)
FIGURE 5-22: BLOCK-ERASE SEQUENCE (SPI)
25119 F08.0
MODE 3 0 1
SCK
SIO(3:0)
CE#
C1 C0
MODE 0
2
A5 A4
MSN
LSN
4
A3 A2
6
A1 A0
Note: MSN = Most Significant Nibble,
LSN = Least Significant Nibble
C[1:0] = D8H
CE#
SO
SI
SCK
ADDR
012345678
ADDR ADDR
D8
HIGH IMPEDANCE
15 16
23
24
31
MODE 0
MODE 3
25119 F58.0
MSB MSB