Datasheet
SST26VF064B / SST26VF064BA
DS20005119G-page 12 2015 Microchip Technology Inc.
4.5.8 I/O CONFIGURATION (IOC)
The I/O Configuration (IOC) bit re-configures the I/O
pins. The IOC bit is set by writing a ‘1’ to Bit 1 of the
Configuration register. When IOC bit is ‘0’ the WP# pin
and HOLD# pin are enabled (SPI or Dual Configuration
setup). When IOC bit is set to ‘1’ the SIO2 pin and SIO3
pin are enabled (SPI Quad I/O Configuration setup).
The IOC bit must be set to ‘1’ before issuing the follow-
ing SPI commands: SQOR (6BH), SQIOR (EBH),
RBSPI (ECH), and SPI Quad page program (32H).
Without setting the IOC bit to ‘1’, those SPI commands
are not valid. The I/O configuration bit does not apply
when in SQI mode. The default at power-up for
SST26VF064B is ‘0’ and for SST26VF064BA is ‘1’.
4.5.9 BLOCK-PROTECTION VOLATILITY
STATE (BPNV)
The Block-Protection Volatility State bit indicates
whether any block has been permanently locked with
the nVWLDR. When no bits in the nVWLDR have been
set, the BPNV is ‘1’; this is the default state from the
factory. When one or more bits in the nVWLDR are set
to ‘1’, the BPNV bit will also be ‘0’ from that point for-
ward, even after power-up.
4.5.10 WRITE-PROTECT ENABLE (WPEN)
The Write-Protect Enable (WPEN) bit is a non-volatile
bit that enables the WP# pin.
The Write-Protect (WP#) pin and the Write-Protect
Enable (WPEN) bit control the programmable hard-
ware write-protect feature. Setting the WP# pin to low,
and the WPEN bit to ‘1’, enables Hardware write-pro-
tection. To disable Hardware write protection, set either
the WP# pin to high or the WPEN bit to ‘0’. There is
latency associated with writing to the WPEN bit. Poll
the BUSY bit in the Status register, or wait T
WPEN
, for
the completion of the internal, self-timed Write opera-
tion. When the chip is hardware write protected, only
Write operations to Block-Protection and Configuration
registers are disabled. See “Hardware Write Protec-
tion” on page 8 and Table 4-1 on page 9 for more infor-
mation about the functionality of the WPEN bit.