Datasheet
SST26VF032B / SST26VF032BA
DS20005218E-page 38 2013-2016 Microchip Technology Inc.
5.36 Non-Volatile Write-Lock Lock-
Down Register (nVWLDR)
The Non-Volatile Write-Lock Lock-Down Register
(nVWLDR) instruction controls the ability to change the
Write-Lock bits in the Block-Protection register. Exe-
cute WREN before initiating the nVWLDR instruction.
To execute nVWLDR, the host drives CE# low, then
sends the nVWLDR command cycle (E8H), followed by
18 cycles of data, and then drives CE# high.
After CE# goes high, the non-volatile bits are pro-
grammed and the programming time-out must com-
plete before any additional commands, other than
Read Status Register, can be entered. Poll the BUSY
bit in the Status register, or wait T
PP
, for the completion
of the internal, self-timed, Write operation. Data inputs
must be most significant bit(s) first.
FIGURE 5-42: WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SQI)
FIGURE 5-43: WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SPI)
20005218 F36.0
MODE 3 0
SCK
SIO(3:0)
CE#
E8
MODE 0
2
H0 L0
MSN
LSN
4
H1 L1
6
H2 L2
8
H3 L3
10
H4 L4
12
H5 L5 HN LN
BPR [m:m-7]
BPR [7:0]
Note: MSN= Most Significant Nibble; LSN = Least Significant Nibble
Write-Lock Lock-Down Register (nVWLDR) m = 79
CE#
SO
SI
SCK
Data Byte0
012345678
Data Byte1 Data Byte2
Data ByteN
E8H
15 16
23 24
31
32
MODE 0
MODE 3
OP Code
20005218 F69.1