Datasheet

SST26VF032B / SST26VF032BA
DS20005218E-page 22  2013-2016 Microchip Technology Inc.
5.12 SPI Dual-Output Read
The SPI Dual-Output Read instruction supports fre-
quencies of up to 104 MHz from 2.7-3.6V and up to 80
MHz from 2.3-3.6V. Initiate SPI Dual-Output Read by
executing an 8-bit command, 3BH, followed by address
bits A[23-0] and a dummy byte. CE# must remain
active low for the duration of the SPI Dual-Output Read
operation. See Figure 5-13 for the SPI Quad Output
Read sequence.
Following the dummy byte, the SST26VF032B/032BA
outputs data from SIO[1:0] starting from the specified
address location. The device continually streams data
output through all addresses until terminated by a low-
to-high transition on CE#. The internal address pointer
automatically increments until the highest memory
address is reached, at which point the address pointer
returns to the beginning of the address space.
FIGURE 5-13: FAST READ, DUAL-OUTPUT SEQUENCE
5.13 SPI Dual I/O Read
The SPI Dual I/O Read (SDIOR) instruction supports
up to 80 MHz frequency. Initiate SDIOR by executing
an 8-bit command, BBH. The device then switches to
2-bit I/O mode for address bits A[23-0], followed by the
Set Mode configuration bits M[7:0]. CE# must remain
active low for the duration of the SPI Dual I/O Read.
See Figure 5-14 for the SPI Dual I/O Read sequence.
Following the Set Mode configuration bits, the
SST26VF032B/032BA outputs data from the specified
address location. The device continually streams data
output through all addresses until terminated by a low-
to-high transition on CE#. The internal address pointer
automatically increments until the highest memory
address is reached, at which point the address pointer
returns to the beginning of the address space.
The Set Mode Configuration bit M[7:0] indicates if the
next instruction cycle is another SPI Dual I/O Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another SDIOR com-
mand, BBH, and does not require the op-code to be
entered again. The host may set the next SDIOR cycle
by driving CE# low, then sending the two-bit wide input
for address A[23:0], followed by the Set Mode configu-
ration bits M[7:0]. After the Set Mode configuration bits,
the device outputs the data starting from the specified
address location. There are no restrictions on address
location access.
When M[7:0] is any value other than AXH, the device
expects the next instruction initiated to be a command
instruction. To reset/exit the Set Mode configuration,
execute the Reset Quad I/O command, FFH. See Fig-
ure 5-15 for the SPI Dual I/O Read sequence when
M[7:0] = AXH.
CE#
SIO0
SCK
012345678
31 32
24
MODE 3
MODE 0
15 16 23
3BH
20005218 F52.3
39 40
41
A[23:16]
A[15:8]
A[7:0]
b6
b5
b6
b5
SIO1
Address
OP Code
Data
Byte 0
Dummy
Data
Byte N
b3
b1
b3
b1
b7
b4
b7
b4
b2
b0
b2
b0
MSB
X
Note: MSB = Most Significant Bit.