Datasheet
SST26VF032B / SST26VF032BA
DS20005218E-page 14 2013-2016 Microchip Technology Inc.
WRSU Suspends Program/Erase B0H X X 0 0 0 104 MHz
/ 80 MHz
WRRE Resumes Program/Erase 30H X X 0 0 0
Protection
RBPR Read Block-Protection
Register
72H X 0 0 1 to18 104 MHz
/ 80 MHz
X0 11 to18
WBPR Write Block-Protection
Register
42H X X 0 0 1 to 18
LBPR Lock Down
Block-Protection
Register
8DH X X 0 0 0
nVWLDR non-Volatile Write Lock-
Down Register
E8H X X 0 0 1 to 18
ULBPR Global Block Protection
Unlock
98HXX 0 0 0
RSID Read Security ID 88H X 2 1 1 to 2048
X 2 3 1 to 2048
PSID Program User
Security ID area
A5H X X 2 0 1 to 256
LSID Lockout Security ID Pro-
gramming
85H X X 0 0 0
1. Command cycle is two clock periods in SQI mode and eight clock periods in SPI mode.
2. Address bits above the most significant bit of each density can be V
IL
or V
IH.
3. Address, Dummy/Mode bits, and Data cycles are two clock periods in SQI and eight clock periods in SPI mode.
4. The max frequency for all instructions is up to 104 MHz from 2.7-3.6V and up to 80 MHz from 2.3-3.6V unless otherwise noted.
5. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
6. Device accepts eight-clock command in SPI mode, or two-clock command in SQI mode.
7. Data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command.
8.Address, Dummy/Mode bits, and data cycles are two clock periods. IOC bit must be set to ‘1’ before issuing the command.
9. Data cycles are four clock periods.
10. Address, Dummy/Mode bits, and Data cycles are four clock periods.
11. Sector Addresses: Use A
MS
- A
12
, remaining address are don’t care, but must be set to V
IL
or V
IH
.
12. Blocks are 64 KByte, 32 KByte, or 8KByte, depending on location. Block Erase Address: A
MS
- A
16
for 64 KByte; A
MS
- A
15
for 32 KByte; A
MS
- A
13
for 8 KByte. Remaining addresses are don’t care, but must be set to V
IL
or V
IH
.
TABLE 5-1: DEVICE OPERATION INSTRUCTIONS FOR SST26VF032B/032BA
Instruction Description
Command
Cycle
1
Mode
Address
Cycle(s)
2, 3
Dummy
Cycle(s)
3
Data
Cycle(s)
3
Max
Freq
4
SPI SQI