Datasheet

512 Kbit SPI Serial Flash

SST25VF512A

Data Sheet

Microchip Technology Company

Product Identification

Memory Organization

The SST25VF512A SuperFlash memory array is organized in 4 KByte sectors with 32 KByte overlay

blocks.

Device Operation

The SST25VF512A is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.

The SPI bus consist of four control lines; Chip Enable (CE#) is used to select the device, and data is

accessed through the Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).

The SST25VF512A supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The differ-

ence between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus mas-

ter is in Stand-by mode and no data is being transferred. The SCK signal is low for Mode 0 and SCK

signal is high for Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the

SCK clock signal and the Serial Data Output (SO) is driven after the falling edge of the SCK clock sig-

nal.

Figure 3: SPI Protocol

Table 2: Product Identification

Address Data

Manufacturer’s ID 00000H BFH

Device ID

SST25VF512A 00001H 48H

T2.0 25090

1264 F02.0

MODE 3

SCK

CE#

MODE 3

DON T CARE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MODE 0MODE 0

HIGH IMPEDANCE

MSB