Datasheet
©2011 Silicon Storage Technology, Inc. DS25071A 12/11
4
32 Mbit SPI Serial Flash
SST25VF032B
Data Sheet
A
Microchip Technology Company
Pin Description
Figure 2: Pin Assignments for 8-Lead SOIC
Table 1: Pin Description
Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI Serial Data Input To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
RY/BY# Ready / Busy pin Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY#
pin.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status reg-
ister.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without reset-
ting the device.
V
DD
Power Supply To provide power supply voltage: 2.7-3.6V
V
SS
Ground
T1.0 25071
1
2
3
4
8
7
6
5
CE#
SO
WP#
V
SS
V
DD
HOLD#
SCK
SI
Top View
1327 8-SOIC P1.0
Note: In AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of-
Write Detection” on page 12. for details.
1
2
3
4
8
7
6
5
CE#
SO
WP#
V
SS
Top View
V
DD
HOLD#
SCK
SI
1327 8-WSON P1.0