Datasheet

©2013 Silicon Storage Technology, Inc. DS20005054C 04/13
4
2 Mbit SPI Serial Flash
SST25VF020B
Data Sheet
Pin Description
Figure 2: Pin Assignments
Table 1: Pin Description
Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI Serial Data Input To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/
BY# pin. See “Hardware End-of-Write Detection” on page 14 for details.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status reg-
ister.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without reset-
ting the device.
V
DD
Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF020B
V
SS
Ground
T1.0 25054
1
2
3
4
8
7
6
5
CE#
SO
WP#
V
SS
V
DD
HOLD#
SCK
SI
Top View
1417 08-soic S2A P1.0
8-Lead SOIC
1
2
3
4
8
7
6
5
CE#
SO
WP#
V
SS
Top View
V
DD
HOLD#
SCK
SI
1417 08-wson QA P2.0
8-Contact WSON
1
2
3
4
8
7
6
5
CE#
SO
WP#
V
SS
Top View
V
DD
HOLD#
SCK
SI
1417 08-uson Q3A P1.0
8-Contact USON