2 Mbit SPI Serial Flash SST25VF020B Data Sheet The 25 series Serial Flash family features a four-wire, SPI compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF020B devices are enhanced with improved operating frequency and even lower power consumption. SST25VF020B SPI serial flash memories are manufactured with SST proprietary, high performance CMOS SuperFlash technology.
Mbit SPI Serial Flash SST25VF020B Data Sheet Product Description The 25 series Serial Flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF020B devices are enhanced with improved operating frequency and even lower power consumption. SST25VF020B SPI serial flash memories are manufactured with SST proprietary, high-performance CMOS SuperFlash technology.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Functional Block Diagram SuperFlash Memory X - Decoder Address Buffers and Latches Y - Decoder I/O Buffers and Data Latches Control Logic Serial Interface CE# SCK SI SO WP# HOLD# 1417 B1.0 Figure 1: Functional Block Diagram ©2013 Silicon Storage Technology, Inc.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Pin Description CE# 1 SO 2 8 VDD 7 HOLD# CE# 1 SO 2 8 VDD 7 HOLD# Top View Top View WP# 3 6 SCK WP# 3 6 SCK VSS 4 5 SI VSS 4 5 SI 8-Contact WSON 8-Lead SOIC 1417 08-wson QA P2.0 1417 08-soic S2A P1.0 CE# 1 SO 2 Top View 8 VDD 7 HOLD# WP# 3 6 SCK VSS 4 5 SI 8-Contact USON 1417 08-uson Q3A P1.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Memory Organization The SST25VF020B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32 KByte overlay blocks and 64 KByte overlay erasable blocks. Device Operation The SST25VF020B is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Hold Operation The HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Status Register The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the Memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 3 describes the function of each bit in the software status register.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Top-Sector Protection/Bottom-Sector Protection The Top-Sector Protection (TSP) and Bottom-Sector Protection (BSP) bits independently indicate whether the highest and lowest sector locations are Write locked or Write accessible. When TSP or BSP is set to ‘1’, the respective sector is Write locked; when set to ‘0’ the respective sector is Write accessible.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Instructions Instructions are used to read, write (Erase and Program), and configure the SST25VF020B. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, WriteStatus-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list of instructions is provided in Table 6.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Read (33 MHz) The Read instruction, 03H, supports up to 33 MHz Read. The device outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is reached.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet High-Speed-Read (80 MHz) The High-Speed-Read instruction supporting up to 80 MHz Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE# must remain active low for the duration of the High-Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence. Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified address location.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Byte-Program instruction.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Auto Address Increment (AAI) Word-Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when multiple bytes or entire memory array is to be programmed. An AAI Word program instruction pointing to a protected memory area will be ignored.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet CE# MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 70 SI MSB HIGH IMPEDANCE SO 1417 EnableSO.0 Figure 8: Enable SO as Hardware RY/BY# During AAI Programming CE# MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 80 SI MSB HIGH IMPEDANCE SO 1417 DisableSO.0 Figure 9: Disable SO as Hardware RY/BY# During AAI Programming ©2013 Silicon Storage Technology, Inc.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet CE# MODE 3 0 0 7 0 7 7 8 15 16 23 24 31 32 39 40 47 0 7 8 15 16 23 SCK MODE 0 SI AD WREN EBSY A A A D0 D1 AD D2 D3 Load AAI command, Address, 2 bytes data SO Check for Flash Busy Status to load next valid1 command CE# cont. 0 7 8 15 16 23 0 7 0 7 0 7 8 15 SCK cont. Dn-1 AD SI cont. WRDI Dn Last 2 Data Bytes DBSY RDSR WRDI followed by DBSY to exit AAI Mode DOUT SO cont.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet 4-KByte Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the WriteEnable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23-A0].
2 Mbit SPI Serial Flash SST25VF020B Data Sheet 32-KByte and 64-KByte Block-Erase The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A BlockErase instruction applied to a protected memory area will be ignored. The 64-KByte Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase instruction is initiated by executing an 8-bit command, 60H or C7H.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Read-Status-Register (RDSR1) The Read-Status-Register 1 (RDSR1) instruction allows reading of the status register 1. CE# must be driven low before the RDSR instruction is entered and remain low until the status data is read. ReadStatus-Register 1 is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 17 for the RDSR instruction sequence.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Write-Disable (WRDI) The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any new Write operations from occurring. The WRDI instruction will not terminate any programming operation in progress. Any program operation in progress may continue up to TBP after executing the WRDI instruction. CE# must be driven high before the WRDI instruction is executed.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Write-Status-Register (WRSR) The Write-Status-Register instruction writes new values to the BP1, BP0, and BPL bits of the status register. CE# must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 20 for EWSR or WREN and WRSR for byte-data input sequences. Executing the Write-Status-Register instruction will be ignored when WP# is low and BPL bit is set to “1”.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet CE# MODE 3 SCK 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MODE 3 MODE 0 MODE 0 50 or 06 SI 01 MSB MSB STATUS STATUS REGISTER REGISTER 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB HIGH IMPEDANCE SO 1417 EWSR1.0 Figure 21:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR) Word-Data Input Sequence The WRSR instruction can either execute a byte-data or a word-data input.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as SST25VF020B and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A23-A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in address 00001H.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Electrical Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Table 11: DC Operating Characteristics Limits Symbol Parameter Min Max Units Test Conditions IDDR Read Current 12 IDDR3 Read Current 20 mA CE#=0.1 VDD/0.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Table 14: AC Operating Characteristics 33 MHz Symbol Parameter Min 80 MHz Max Min Max Units 80 MHz FCLK1 Serial Clock Frequency TSCKH Serial Clock High Time 13 6 ns TSCKL Serial Clock Low Time 13 6 ns TSCKR 2 33 Serial Clock Rise Time (Slew Rate) 0.1 0.1 V/ns TSCKF Serial Clock Fall Time (Slew Rate) 0.1 0.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet TCPH CE# TCHH TCES TCEH TSCKF TCHS SCK TDS SI SO TDH TSCKR MSB LSB HIGH-Z HIGH-Z 1417 SerIn.0 Figure 24:Serial Input Timing Diagram CE# TSCKH TSCKL SCK TOH TCLZ SO TCHZ LSB MSB TV SI 1417 SerOut.0 Figure 25:Serial Output Timing Diagram CE# THHH THHS THLS SCK THLH THZ TLZ SO SI HOLD# 1417 Hold.0 Figure 26:Hold Timing Diagram ©2013 Silicon Storage Technology, Inc.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Power-Up Specifications All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0v - 3.0V in less than 300 ms). See Table 15 and Figure 27 for more information. Table 15: Recommended System Power-up Timings Symbol Parameter Minimum Units TPU-READ1 VDD Min to Read Operation 100 µs VDD Min to Write Operation 100 µs TPU-WRITE 1 T15.0 25054 1.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Table 16: Recommended Power-up/-down Limits Limits Symbol Parameter Min Max Units TPF VDD Falling Time 1 100 ms/V TPR VDD Rising Time 0.033 100 ms/V TOFF VDD Off Time VOFF VDD Off Level 100 Conditions ms 0.3 V 0V (recommended) T16.0 25054 VDD VOFF GND TOFF 1417 F28.0 Figure 28:Recommended Power-up/-down Waveform ©2013 Silicon Storage Technology, Inc.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet VIHT VHT INPUT? VHT REFERENCE POINTS OUTPUT VLT VLT VILT 1417 IORef.0 AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VHT - VHIGH Test VLT - VLOW Test VIHT - VINPUT HIGH Test Figure 29:AC Input/Output Reference Waveforms TO TESTER TO DUT CL 1417 TstLd.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Product Ordering Information SST 25 VF 020B - 80 - 4C - SAE XX XX XXXX - XX - XX - XXX Environmental Attribute E1 = non-Pb Package Modifier A = 8 leads or contacts Package Type S = SOIC 150 mil body width Q = WSON(6mm x 5mm) Q3 = USON (3mm x 2mm) Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles2 Operating Frequency 80 = 80 MHz Device Density 020 = 2 Mbit Voltage V = 2.7-3.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Packaging Diagrams Pin #1 Identifier SIDE VIEW TOP VIEW 7° 4 places 0.51 0.33 5.0 4.8 1.27 BSC END VIEW 45° 0.25 0.10 4.00 3.80 1.75 1.35 6.20 5.80 7° 4 places 0.25 0.19 Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet TOP VIEW SIDE VIEW BOTTOM VIEW Pin #1 0.2 Pin #1 Corner 1.27 BSC 5.00 ± 0.10 0.076 4.0 0.48 0.35 3.4 0.70 0.50 0.05 Max 6.00 ± 0.10 0.80 0.70 Note: 1. All linear dimensions are in millimeters (max/min). 2. Untoleranced dimensions (shown with box surround) are nominal target dimensions. 3. The external paddle is electrically connected to the 1mm die back-side and possibly to certain VSS leads.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet 2.45 3.00 ±0.10 0.25 ±0.05 Pin #1 (laser engraved see note 2) See notes 3 &4 Pin # 1 1.60 2.00 ±0.10 0.5 BSC 0.15 max 0.08 0.05 Max 0.60 0.45 0.40 ±0.05 0.2 0.35 ±0.05 1mm 8-uson-2x2-Q3A-1.1 Note: 1. 2. 3. 4. 5. 6. Similar to JEDEC JEP95 MO-252 variant U2030D, though number of contacts and some dimensions may be different. The topside pin #1 indicator is laser engraved; its approximate shape and location is as shown.
2 Mbit SPI Serial Flash SST25VF020B Data Sheet Table 17: Revision History Revision 00 01 02 03 A B C Description • • • • • • • • • • • • • • • Initial release of data sheet Updated Table 4 on page 7 Added Figure 28 and Table 16 on page 30 Changed TDS value in Table 14 on page 27 Updated SST address on page 33 Changed document status to “Data Sheet” Updated “Auto Address Increment (AAI) Word-Program”, “End-ofWrite Detection”, and “Hardware End-of-Write Detection” on page 14.
