Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsIntegrated Circuits (ICs)SOIC 8 2 Bit 256 K x 8

Microchip Technology Company

Not Recommended for New Designs

www.microchip.com

Features

• Single 2.7-3.6V Read and Write Operations

• Serial Interface Architecture

– SPI Compatible: Mode 0 and Mode 3

• 20 MHz Max Clock Frequency

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption:

– Active Read Current: 7 mA (typical)

– Standby Current: 8 µA (typical)

• Flexible Erase Capability

– Uniform 4 KByte sectors

– Uniform 32 KByte overlay blocks

• Fast Erase and Byte-Program:

– Chip-Erase Time: 70 ms (typical)

– Sector- or Block-Erase Time: 18 ms (typical)

– Byte-Program Time: 14 µs (typical)

• Auto Address Increment (AAI) Programming

– Decrease total chip programming time over Byte-Pro-

gram operations

• End-of-Write Detection

– Software Status

• Hold Pin (HOLD#)

– Suspends a serial sequence to the memory

without deselecting the device

• Write Protection (WP#)

– Enables/Disables the Lock-Down function of the status

• Software Write Protection

– Write protection through Block-Protection bits in status

• Temperature Range

– Commercial: 0°C to +70°C

– Industrial: -40°C to +85°C

– Extended: -20°C to +85°C

• Packages Available

– 8-lead SOIC 150 mil body width

– 8-contact WSON (5mm x 6mm)

• All non-Pb (lead-free) devices are RoHS compliant

2 Mbit SPI Serial Flash

SST25VF020

SST's serial flash family features a four-wire, SPI-compatible interface that allows

for a low pin-count package occupying less board space and ultimately lowering

total system costs. SST25VF020 SPI serial flash memory is manufactured with

SST proprietary, high performance CMOS SuperFlash Technology. The split-gate

cell design and thick-oxide tunneling injector attain better reliability and manufac-

turability compared with alternate approaches.

Not recommended for new designs.

Please use SST25VF020B

Summary of content (27 pages)

PAGE 1
Not recommended for new designs. Please use SST25VF020B 2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs SST's serial flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package occupying less board space and ultimately lowering total system costs. SST25VF020 SPI serial flash memory is manufactured with SST proprietary, high performance CMOS SuperFlash Technology.
PAGE 2
Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Product Description The SST serial flash family features a four-wire, SPI-compatible interface that allows for a low pincount package occupying less board space and ultimately lowering total system costs. SST25VF020 SPI serial flash memories are manufactured with SST’s proprietary, high performance CMOS SuperFlash Technology.
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2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Block Diagram SuperFlash Memory X - Decoder Address Buffers and Latches Y - Decoder I/O Buffers and Data Latches Control Logic Serial Interface 1231 B1.0 CE# SCK SI SO WP# HOLD# Figure 1: Functional Block Diagram ©2011 Silicon Storage Technology, Inc.
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2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Pin Description 8 VDD 7 HOLD# 3 6 SCK 4 5 SI CE# 1 SO 2 CE# 1 8 VDD SO 2 7 HOLD# WP# 3 6 SCK WP# VSS 4 5 SI VSS Top View Top View 1231 08-wson P2.0 1231 08-soic P1.0 8-lead SOIC 8-contact WSON Figure 2: Pin Assignments Table 1: Pin Description Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface.
PAGE 5
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Memory Organization The SST25VF020 SuperFlash memory array is organized in 4 KByte sectors with 32 KByte overlay blocks. Device Operation The SST25VF020 is accessed through the SPI (Serial Peripheral Interface) bus compatible protocol.
PAGE 6
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Hold Operation HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.
PAGE 7
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Status Register The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress.
PAGE 8
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Block Protection (BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table 4, to be software protected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the BlockProtect-Lock (BPL) bit is 0.
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2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Instructions Instructions are used to Read, Write (Erase and Program), and configure the SST25VF020. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first.
PAGE 10
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs 10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both instructions effective. 11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H.
PAGE 11
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed.
PAGE 12
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Auto Address Increment (AAI) Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when the entire memory array is to be programmed. An AAI program instruction pointing to a protected memory area will be ignored.
PAGE 13
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the WriteEnable (WREN) instruction must be executed. CE# must remain active low for the duration of the any command sequence.
PAGE 14
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase instruction is initiated by executing an 8-bit command, 60H.
PAGE 15
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Write-Enable (WREN) The Write-Enable (WREN) instruction sets the Write-Enable-Latch bit to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE# must be driven high before the WREN instruction is executed. CE# MODE 3 SCK 0 1 2 3 4 5 6 7 MODE 0 06 SI MSB SO HIGH IMPEDANCE 1231 F11.
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2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Write-Status-Register (WRSR) The Write-Status-Register instruction works in conjunction with the Enable-Write-Status-Register (EWSR) instruction to write new values to the BP1, BP0, and BPL bits of the status register. The WriteStatus-Register instruction must be executed immediately after the execution of the Enable-Write-Status-Register instruction (very next instruction bus cycle).
PAGE 17
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Read-ID The Read-ID instruction identifies the device as SST25VF020 and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A23A0]. Following the Read-ID instruction, the manufacturer’s ID is located in address 00000H and the device ID is located in address 00001H.
PAGE 18
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Electrical Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
PAGE 19
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Table 10:Recommended System Power-up Timings Symbol Parameter Minimum Units TPU-READ1 VDD Min to Read Operation 10 µs VDD Min to Write Operation 10 µs TPU-WRITE 1 T10.0 25078 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
PAGE 20
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Table 13:AC Operating Characteristics VDD = 2.7-3.
PAGE 21
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs TCPH CE# TCES TCHH TSCKF TCEH TCHS SCK TDS SI SO TDH TSCKR MSB LSB HIGH-Z HIGH-Z 1231 F15.0 Figure 16:Serial Input Timing Diagram CE# TSCKL TSCKH SCK TOH TCLZ SO MSB TCHZ LSB TV SI 1231 F16.0 Figure 17:Serial Output Timing Diagram ©2011 Silicon Storage Technology, Inc.
PAGE 22
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs CE# THHH THLS THHS SCK THZ THLH TLZ SO SI HOLD# 1231 F17.0 Figure 18:Hold Timing Diagram VDD VDD Max Chip selection is not allowed. All commands are rejected by the device. VDD Min TPU-READ TPU-WRITE Device fully accessible Time 1231 F18.0 Figure 19:Power-up Timing Diagram ©2011 Silicon Storage Technology, Inc.
PAGE 23
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs VIHT VHT INPUT VHT REFERENCE POINTS OUTPUT VLT VLT VILT 1231 F19.1 AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement reference points for inputs and outputs are VHT (0.7VDD) and VLT (0.3VDD). Input rise and fall times (10%  90%) are <5 ns.
PAGE 24
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Product Ordering Information SST 25 VF XX XX 020 XXX - 20 XX - 4I XX - QAE XXX Environmental Attribute E1 = non-Pb Package Modifier A = 8 leads or contacts Package Type S = SOIC 150 mil body width Q = WSON Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C E = Extended = -20°C to +85°C Minimum Endurance 4 = 10,000 cycles Operating Frequency 20 = 20 MHz Device Density 020 =
PAGE 25
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Packaging Diagrams Pin #1 Identifier TOP VIEW SIDE VIEW 7° 4 places 0.51 0.33 5.0 4.8 1.27 BSC END VIEW 45° 0.25 0.10 4.00 3.80 1.75 1.35 6.20 5.80 7° 4 places 0.25 0.19 Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.
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2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs TOP VIEW SIDE VIEW BOTTOM VIEW Pin #1 0.2 Pin #1 Corner 1.27 BSC 5.00 ± 0.10 0.076 4.0 0.48 0.35 3.4 0.70 0.50 0.05 Max 6.00 ± 0.10 0.80 0.70 Note: 1. All linear dimensions are in millimeters (max/min). 2. Untoleranced dimensions (shown with box surround) are nominal target dimensions. 3. The external paddle is electrically connected to the die back-side and possibly to certain VSS leads.
PAGE 27
2 Mbit SPI Serial Flash SST25VF020 A Microchip Technology Company Not Recommended for New Designs Table 14:Revision History Revision Description 00 • 01 • • • • • • 02 03 04 05 06 07 • • • • • A • • • Date Initial release of S71231 (2 Mbit and 4 Mbit parts were originally described in data sheet S71192) Updated Figures 3, 5 - 15: Aligned SI waveform with rising edge of clock Added new 8-SOIC (S2A) package and associated MPNs 2004 Data Book Updated the Package Outline for S2A Added Extended te