Datasheet
©2011 Silicon Storage Technology, Inc. DS25044A 08/11
9
16 Mbit SPI Serial Flash
SST25VF016B
Data Sheet
A
Microchip Technology Company
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25VF016B. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-
ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-
Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed
first. The complete list of instructions is provided in Table 5. All instructions are synchronized off a high
to low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most signif-
icant bit. CE# must be driven low before an instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instruc-
tions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device to standby mode. Instruction commands
(Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions
Instruction Description Op Code Cycle
1
1. One bus cycle is eight clock periods.
Address
Cycle(s)
2
Dummy
Cycle(s)
Data
Cycle(s)
Maximum
Frequency
Read Read Memory at 25 MHz 0000 0011b (03H) 3 0 1 to 25 MHz
High-Speed
Read
Read Memory at 80 MHz 0000 1011b (0BH) 3 1 1 to 80 MHz
4 KByte Sec-
tor-Erase
3
Erase 4 KByte of
memory array
0010 0000b (20H) 3 0 0 80 MHz
32 KByte
Block-Erase
4
Erase 32 KByte block
of memory array
0101 0010b (52H) 3 0 0 80 MHz
64 KByte
Block-Erase
5
Erase 64 KByte block
of memory array
1101 1000b (D8H) 3 0 0 80 MHz
Chip-Erase Erase Full Memory Array 0110 0000b (60H)
or
1100 0111b (C7H)
0 0 0 80 MHz
Byte-Program To Program One Data Byte 0000 0010b (02H) 3 0 1 80 MHz
AAI-Word-Pro-
gram
6
Auto Address Increment
Programming
1010 1101b (ADH) 3 0 2 to 80 MHz
RDSR
7
Read-Status-Register 0000 0101b (05H) 0 0 1 to 80 MHz
EWSR Enable-Write-Status-Reg-
ister
0101b 0000b
(50H)
0 0 0 80 MHz
WRSR Write-Status-Register 0000 0001b (01H) 0 0 1 80 MHz
WREN Write-Enable 0000 0110b (06H) 0 0 0 80 MHz
WRDI Write-Disable 0000 0100b (04H) 0 0 0 80 MHz
RDID
8
Read-ID 1001 0000b (90H)
or
1010 1011b (ABH)
301to 80 MHz
JEDEC-ID JEDEC ID read 1001 1111b (9FH) 0 0 3 to 80 MHz
EBSY Enable SO to output RY/BY#
status during AAI program-
ming
0111 0000b (70H) 0 0 0 80 MHz
DBSY Disable SO as RY/BY#
status during AAI program-
ming
1000 0000b (80H) 0 0 0 80 MHz
T5.0 25044