Datasheet

©2011 Silicon Storage Technology, Inc. S725081A 10/11
9
1 Mbit SPI Serial Flash
SST25VF010A
Data Sheet
A
Microchip Technology Company
Instructions
Instructions are used to Read, Write (Erase and Program), and configure the SST25VF010A. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-
ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or
Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list
of the instructions is provided in Table 6. All instructions are synchronized off a high to low transition of
CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must
be driven low before an instruction is entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high
transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction
in progress and return the device to the standby mode. Instruction commands (Op Code), addresses,
and data are all input from the most significant bit (MSB) first.
Table 6: Device Operation Instructions
1
1. A
MS
= Most Significant Address
A
MS
=A
16
for SST25VF010A
Address bits above the most significant bit of each density can be V
IL
or V
IH
Bus Cycle
2
2. One bus cycle is eight clock periods.
123 456
Cycle Type/
Operation
3,4
3. Operation: S
IN
= Serial In, S
OUT
= Serial Out
4. X = Dummy Input Cycles (V
IL
or V
IH
); - = Non-Applicable Cycles (Cycles are not necessary)
S
IN
S
OUT
S
IN
S
OUT
S
IN
S
OUT
S
IN
S
OUT
S
I
N
S
OUT
S
I
N
S
OUT
Read (20 MHz) 03H Hi-Z A
23
-
A
16
Hi-Z A
15
-
A
8
Hi-Z A
7
-A
0
Hi-Z X D
OUT
High-Speed-Read (33
MHz)
0BH Hi-Z A
23
-
A
16
Hi-Z A
15
-
A
8
Hi-Z A
7
-A
0
Hi-Z X X X D
OUT
Sector-Erase
5,6
5. Sector addresses: use A
MS
-A
12
, remaining addresses can be V
IL
or V
IH
20H Hi-Z A
23
-
A
16
Hi-Z A
15
-
A
8
Hi-Z A
7
-A
0
Hi-Z - -
Block-Erase
5,7
52H
or
D8H
Hi-Z A
23
-
A
16
Hi-Z A
15
-
A
8
Hi-Z A
7
-A
0
Hi-Z - -
Chip-Erase
6
60H
or
C7H
Hi-Z - - - - - - - -
Byte-Program
6
02H Hi-Z A
23
-
A
16
Hi-Z A
15
-
A
8
Hi-Z A
7
-A
0
Hi-Z D
IN
Hi-Z Hi-Z
Auto Address Increment
(AAI) Program
6,8
AFH Hi-Z A
23
-
A
16
Hi-Z A
15
-
A
8
Hi-Z A
7
-A
0
Hi-Z D
IN
Hi-Z Hi-Z
Read-Status-Register
(RDSR)
05H Hi-Z X D
OUT
- Note
9
- Note
9
- Note
9
Note
9
Enable-Write-Status-Regis-
ter
(EWSR)
10
50H Hi-Z - - - - - - - -
Write-Status-Register
(WRSR)
10
01H Hi-Z Data Hi-Z - - -. - - -
Write-Enable (WREN) 06H Hi-Z - - - - - - - -
Write-Disable (WRDI) 04H Hi-Z - - - - - - - -
Read-ID 90H
or
ABH
Hi-Z 00H Hi-Z 00H Hi-Z ID
Addr
11
Hi-Z X D
OUT
12
D
OUT
1
2
T6.0 25081