User manual

8-PIN SOIC/MSOP/TSSOP/DIP
EVALUATION BOARD USERS GUIDE
© 2005 Microchip Technology Inc. DS51544A-page 35
Appendix D. Rev. 1 PCB Errata
D.1 INTRODUCTION
This appendix documents the issues with the Rev 1 PCB. The Rev 2 PCB fixes these
issues.
D.2 REV 1 PCB ISSUES
There are two issues with the Rev 1 PCB. These are:
1. VDD and VSS vias near each pad are No Connects (they should have been
connected to the appropriate power or ground plane). See Figure D-1 shows the
location of these vias that are No Connects. Figure D-3 shows alternate
connections that can be made.
2. The silk-screen on the bottom layer was not processed. This was anly intended
for indicating the circuit of the board. This can be done with a sticky label.
Figure D-2 shows how to determine the PCB revision.
FIGURE D-1: 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board Gerber - Top Layer + Silk-Screen.
Although these vias were intended to be connected to either the V
DD
or V
SS
plane (as indicated), they
are actually no connects. Rev 2 of the board addresses this.