Datasheet

 2009-2013 Microchip Technology Inc. DS60001156H-page 51
PIC32MX5XX/6XX/7XX
The MIPS
®
architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.
In addition to the HI/LO targeted operations, the
MIPS32
®
architecture also defines a multiply instruc-
tion, MUL, which places the least significant results in
the primary register file instead of the HI/LO register
pair. By avoiding the explicit MFLO instruction required
when using the LO register, and by supporting multiple
destination registers, the throughput of multiply-inten-
sive operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
3.2.3 SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS
®
architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configura-
tion information, such as presence of options like
MIPS16e
®
, is also available by accessing the CP0
registers, listed in Table 3-2.
TABLE 3-2: COPROCESSOR 0 REGISTERS
Register
Number
Register
Name
Function
0-6 Reserved Reserved.
7 HWREna Enables access via the RDHWR instruction to selected hardware registers.
8 BadVAddr
(1)
Reports the address for the most recent address-related exception.
9 Count
(1)
Processor cycle count.
10 Reserved Reserved.
11 Compare
(1)
Timer interrupt control.
12 Status
(1)
Processor status and control.
12 IntCtl
(1)
Interrupt system status and control.
12 SRSCtl
(1)
Shadow register set status and control.
12 SRSMap
(1)
Provides mapping from vectored interrupt to a shadow set.
13 Cause
(1)
Cause of last general exception.
14 EPC
(1)
Program counter at last exception.
15 PRId Processor identification and revision.
15 Ebase Exception vector base register.
16 Config Configuration register.
16 Config1 Configuration Register 1.
16 Config2 Configuration Register 2.
16 Config3 Configuration Register 3.
17-22 Reserved Reserved.
23 Debug
(2)
Debug control and exception status.
24 DEPC
(2)
Program counter at last debug exception.
25-29 Reserved Reserved.
30 ErrorEPC
(1)
Program counter at last error.
31 DESAVE
(2)
Debug handler scratchpad register.
Note 1: Registers used in exception processing.
2: Registers used during debug.