Datasheet

PIC32MX5XX/6XX/7XX
DS60001156H-page 440  2009-2013 Microchip Technology Inc.
Output Compare................................................................ 209
P
Packaging .........................................................................409
Details ....................................................................... 411
Marking ..................................................................... 409
Parallel Master Port (PMP) ...............................................229
PIC32 Family USB Interface Diagram...............................174
Pinout I/O Descriptions (table) ............................................ 34
Power-on Reset (POR)
and On-Chip Voltage Regulator................................350
Power-Saving Features..................................................... 337
CPU Halted Methods ................................................337
Operation ..................................................................337
with CPU Running..................................................... 337
Prefetch Cache .................................................................147
Program Flash Memory
Wait State Characteristics.........................................371
R
Reader Response .............................................................444
Real-Time Clock and Calendar (RTCC)............................ 237
Register Maps............................................................. 62–116
Registers
AD1CHS (ADC Input Select) .................................... 253
AD1CON1 (ADC Control 1) ......................................249
AD1CON2 (ADC Control 2) ......................................251
AD1CON3 (ADC Control 3) ......................................252
AD1CSSL (ADC Input Scan Select) .........................254
ALRMDATE (Alarm Date Value)............................... 245
ALRMTIME (Alarm Time Value) ...............................244
BMXBOOTSZ (Boot Flash (IFM) Size) .....................122
BMXCON (Bus Matrix Configuration) ....................... 117
BMXDKPBA (Data RAM Kernel Program
Base Address) ..................................................118
BMXDRMSZ (Data RAM Size) .................................121
BMXDUDBA (Data RAM User Data Base Address) . 119
BMXDUPBA (Data RAM User Program
Base Address) ..................................................120
BMXPFMSZ (Program Flash (PFM) Size) ................ 122
BMXPUPBA (Program Flash (PFM) User Program
Base Address) ..................................................121
CHEACC (Cache Access) ........................................149
CHECON (Cache Control) ........................................ 148
CHEHIT (Cache Hit Statistics) .................................. 154
CHELRU (Cache LRU) ............................................. 153
CHEMIS (Cache Miss Statistics) .............................. 154
CHEMSK (Cache TAG Mask)...................................151
CHETAG (Cache TAG)............................................. 150
CHEW0 (Cache Word 0)...........................................151
CHEW1 (Cache Word 1)...........................................152
CHEW2 (Cache Word 2)...........................................152
CHEW3 (Cache Word 3)...........................................153
CiCFG (CAN Baud Rate Configuration)....................258
CiCON (CAN Module Control) .................................. 256
CiFIFOBA (CAN Message Buffer Base Address) ..... 283
CiFIFOCINn (CAN Module Message Index Register ‘n’)
288
CiFIFOCONn (CAN FIFO Control Register ‘n’).........284
CiFIFOINTn (CAN FIFO Interrupt Register ‘n’) .........286
CiFIFOUAn (CAN FIFO User Address Register ‘n’).. 288
CiFLTCON0 (CAN Filter Control 0)...........................266
CiFLTCON1 (CAN Filter Control 1)...........................268
CiFLTCON2 (CAN Filter Control 2)...........................270
CiFLTCON3 (CAN Filter Control 3)...........................272
CiFLTCON4 (CAN Filter Control 4) .......................... 274
CiFLTCON5 (CAN Filter Control 5) .......................... 276
CiFLTCON6 (CAN Filter Control 6) .......................... 278
CiFLTCON7 (CAN Filter Control 7) .......................... 280
CiFSTAT (CAN FIFO Status).................................... 263
CiINT (CAN Interrupt) ............................................... 260
CiRXFn (CAN Acceptance Filter ‘n’)......................... 282
CiRXMn (CAN Acceptance Filter Mask ‘n’) .............. 265
CiRXOVF (CAN Receive FIFO Overflow Status) ..... 264
CiTMR (CAN Timer) ................................................. 264
CiTREC (CAN Transmit/Receive Error Count)......... 263
CiVEC (CAN Interrupt Code).................................... 262
CMSTAT (Comparator Control Register).................. 333
CMxCON (Comparator ’x’ Control)........................... 332
CNCON (Change Notice Control)............................. 195
CVRCON (Comparator Voltage Reference Control) 336
DCHxCON (DMA Channel ’x’ Control) ..................... 163
DCHxCPTR (DMA Channel ’x’ Cell Pointer)............. 170
DCHxCSIZ (DMA Channel ’x’ Cell-Size) .................. 170
DCHxDAT (DMA Channel ’x’ Pattern Data).............. 171
DCHxDPTR (Channel ’x’ Destination Pointer).......... 169
DCHxDSA (DMA Channel ’x’ Destination
Start Address)................................................... 167
DCHxDSIZ (DMA Channel ’x’ Destination Size)....... 168
DCHxECON (DMA Channel ’x’ Event Control)......... 164
DCHxINT (DMA Channel ’x’ Interrupt Control) ......... 165
DCHxSPTR (DMA Channel ’x’ Source Pointer)........ 169
DCHxSSA (DMA Channel ’x’ Source Start Address) 167
DCHxSSIZ (DMA Channel ’x’ Source Size).............. 168
DCRCCON (DMA CRC Control)............................... 160
DCRCDATA (DMA CRC Data)................................. 162
DCRCXOR (DMA CRCXOR Enable) ....................... 162
DDPCON (Debug Data Port Control) ....................... 351
DEVCFG0 (Device Configuration Word 0................. 340
DEVCFG1 (Device Configuration Word 1................. 342
DEVCFG2 (Device Configuration Word 2................. 344
DEVCFG3 (Device Configuration Word 3................. 346
DEVID (Device and Revision ID).............................. 347
DMAADDR (DMA Address)...................................... 159
DMACON (DMA Controller Control) ......................... 158
DMASTAT (DMA Status).......................................... 159
EMAC1CFG1 (Ethernet Controller MAC Configuration 1)
313
EMAC1CFG2 (Ethernet Controller MAC Configuration 2)
314
EMAC1CLRT (Ethernet Controller MAC Collision Win-
dow/Retry Limit)................................................ 318
EMAC1IPGR (Ethernet Controller MAC Non-Back-to-
Back Interpacket Gap)...................................... 317
EMAC1IPGT (Ethernet Controller MAC Back-to-Back In-
terpacket Gap).................................................. 316
EMAC1MADR (Ethernet Controller MAC MII Manage-
ment Address) .................................................. 324
EMAC1MAXF (Ethernet Controller MAC Maximum
Frame Length).................................................. 319
EMAC1MCFG (Ethernet Controller MAC MII Manage-
ment Configuration).......................................... 322
EMAC1MCMD (Ethernet Controller MAC MII Manage-
ment Command)............................................... 323
EMAC1MIND (Ethernet Controller MAC MII Manage-
ment Indicators)................................................ 326
EMAC1MRDD (Ethernet Controller MAC MII Manage-
ment Read Data) .............................................. 325
EMAC1MWTD (Ethernet Controller MAC MII Manage-
ment Write Data) .............................................. 325