Datasheet

2009-2013 Microchip Technology Inc. DS60001156H-page 43
PIC32MX5XX/6XX/7XX
AEMDC 30 71 C11 A46 O
Alternate Ethernet Management Data
clock
(2)
AEMDIO 49 68 E9 B37 I/O Alternate Ethernet Management Data
(2)
TRCLK 91 C5 B51 O Trace clock
TRD0 97 A3
B55
O Trace Data bits 0-3
TRD1 96 C3 A65 O
TRD2 95 C4 B54 O
TRD3 92 B5 A62 O
PGED1 16 25 K2 B14 I/O ST
Data I/O pin for Programming/
Debugging Communication Channel 1
PGEC1 15 24 K1 A15 I ST
Clock input pin for Programming/
Debugging Communication Channel 1
PGED2 18 27 J3 B16 I/O ST
Data I/O pin for Programming/
Debugging Communication Channel 2
PGEC2 17 26 L1 A20 I ST
Clock input pin for Programming/
Debugging Communication Channel 2
MCLR
713F1
B7
I/P ST
Master Clear (Reset) input. This pin is
an active-low Reset to the device.
AVDD 19 30 J4 A22 P P
Positive supply for analog modules.
This pin must be connected at all times.
AV
SS 20 31 L3 B18 P P Ground reference for analog modules
V
DD
10, 26, 38,
57
2, 16, 37,
46, 62, 86
A7, C2,
C9, E5,
K8, F8,
G5, H4,
H6
A10, A14,
A30, A41,
A48, A59,
B1, B21,
B53
P—
Positive supply for peripheral logic and
I/O pins
V
CAP 56 85 B7 B48 P Capacitor for Internal Voltage Regulator
V
SS 9, 25, 41
15, 36, 45,
65, 75
A8, B10,
D4, D5,
E7, F5,
F10, G6,
G7, H3
A3, A25,
A43, A63,
B8, B12,
B25, B41,
B46
P—
Ground reference for logic and I/O pins.
This pin must be connected at all times.
V
REF+ 16 29 K3 B17 I Analog Analog voltage reference (high) input
VREF- 15 28 L2 A21 I Analog Analog voltage reference (low) input
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
(1)
Pin
Type
Buffer
Type
Description
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
TFBGA
124-pin
VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the Pin Diagrams section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.