Datasheet

PIC32MX5XX/6XX/7XX
DS60001156H-page 42  2009-2013 Microchip Technology Inc.
ERXD0 61 41 J7 B23 I ST Ethernet Receive Data 0
(2)
ERXD1 60 42 L7 A28 I ST Ethernet Receive Data 1
(2)
ERXD2 59 43 K7 B24 I ST Ethernet Receive Data 2
(2)
ERXD3 58 44 L8
A29
I ST Ethernet Receive Data 3
(2)
ERXERR 64 35 J5 B20 I ST Ethernet receive error input
(2)
ERXDV 62 12 F2 A8 I ST Ethernet receive data valid
(2)
ECRSDV 62 12 F2 A8 I ST Ethernet carrier sense data valid
(2)
ERXCLK 63 14 F3 A9 I ST Ethernet receive clock
(2)
EREFCLK 63 14 F3 A9 I ST Ethernet reference clock
(2)
ETXD0 2 88 A6 A60 O — Ethernet Transmit Data 0
(2)
ETXD1 3 87 B6 B49 O — Ethernet Transmit Data 1
(2)
ETXD2 43 79 A9 B43 O — Ethernet Transmit Data 2
(2)
ETXD3 42 80 D8 A54 O — Ethernet Transmit Data 3
(2)
ETXERR 54 89 E6 B50 O — Ethernet transmit error
(2)
ETXEN 1 83 D7 B45 O — Ethernet transmit enable
(2)
ETXCLK 55 84 C7 A56 I ST Ethernet transmit clock
(2)
ECOL 44 10 E3 A7 I ST Ethernet collision detect
(2)
ECRS 45 11 F4 B6 I ST Ethernet carrier sense
(2)
EMDC 30 71 C11 A46 O — Ethernet management data clock
(2)
EMDIO 49 68 E9 B37 I/O — Ethernet management data
(2)
AERXD0 43 18 G1 A11 I ST Alternate Ethernet Receive Data 0
(2)
AERXD1 42 19 G2 B10 I ST Alternate Ethernet Receive Data 1
(2)
AERXD2 — 28 L2 A21 I ST Alternate Ethernet Receive Data 2
(2)
AERXD3 — 29 K3 B17 I ST Alternate Ethernet Receive Data 3
(2)
AERXERR 55 1 B2 A2 I ST Alternate Ethernet receive error input
(2)
AERXDV — 12 F2 A8 I ST Alternate Ethernet receive data valid
(2)
AECRSDV 44 12 F2 A8 I ST
Alternate Ethernet carrier sense data
valid
(2)
AERXCLK — 14 F3 A9 I ST Alternate Ethernet receive clock
(2)
AEREFCLK 45 14 F3 A9 I ST Alternate Ethernet reference clock
(2)
AETXD0 59 47 L9 B26 O — Alternate Ethernet Transmit Data 0
(2)
AETXD1 58 48 K9 A31 O — Alternate Ethernet Transmit Data 1
(2)
AETXD2 — 44 L8 A29 O — Alternate Ethernet Transmit Data 2
(2)
AETXD3 — 43 K7 B24 O — Alternate Ethernet Transmit Data 3
(2)
AETXERR — 35 J5 B20 O — Alternate Ethernet transmit error
(2)
AETXEN 54 67 E8 A44 O — Alternate Ethernet transmit enable
(2)
AETXCLK — 66 E11 B36 I ST Alternate Ethernet transmit clock
(2)
AECOL — 42 L7 A28 I ST Alternate Ethernet collision detect
(2)
AECRS — 41 J7 B23 I ST Alternate Ethernet carrier sense
(2)
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
(1)
Pin
Type
Buffer
Type
Description
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
TFBGA
124-pin
VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.