Datasheet

 2009-2013 Microchip Technology Inc. DS60001156H-page 41
PIC32MX5XX/6XX/7XX
PMD0 60 93 A4
B52
I/O TTL/ST Parallel Master Port data
(Demultiplexed Master mode) or
address/data (Multiplexed Master
modes)
PMD1 61 94 B4 A64 I/O TTL/ST
PMD2 62 98 B3 A66 I/O TTL/ST
PMD3 63 99 A2 B56 I/O TTL/ST
PMD4 64 100 A1 A67 I/O TTL/ST
PMD5 1 3 D3 B2 I/O TTL/ST
PMD6 2 4 C1 A4 I/O TTL/ST
PMD7 3 5 D2 B3 I/O TTL/ST
PMD8 — 90 A5 A61 I/O TTL/ST
PMD9 — 89 E6 B50 I/O TTL/ST
PMD10 — 88 A6 A60 I/O TTL/ST
PMD11 — 87 B6 B49 I/O TTL/ST
PMD12 — 79 A9 B43 I/O TTL/ST
PMD13 — 80 D8 A54 I/O TTL/ST
PMD14 — 83 D7 B45 I/O TTL/ST
PMD15 — 84 C7 A56 I/O TTL/ST
PMALL 30 44 L8 A29 O —
Parallel Master Port address latch
enable low byte (Multiplexed Master
modes)
PMALH 29 43 K7 B24 O —
Parallel Master Port address latch
enable high byte (Multiplexed Master
modes)
PMRD 53 82 B8 A55 O — Parallel Master Port read strobe
PMWR 52 81 C8 B44 O — Parallel Master Port write strobe
V
BUS 34 54 H8 A37 I Analog USB bus power monitor
V
USB3V3 35 55 H9 B30 P —
USB internal transceiver supply. If the
USB module is not used, this pin must
be connected to V
DD.
V
BUSON 11 20 H1 A12 O —
USB Host and OTG bus power control
output
D+ 37 57 H10 B31 I/O Analog USB D+
D- 36 56 J11 A38 I/O Analog USB D-
USBID 33 51 K10 A35 I ST USB OTG ID detect
C1RX 58 87 B6 B49 I ST CAN1 bus receive pin
C1TX 59 88 A6 A60 O — CAN1 bus transmit pin
AC1RX 32 40 K6 A27 I ST Alternate CAN1 bus receive pin
AC1TX 31 39 L6 B22 O — Alternate CAN1 bus transmit pin
C2RX 29 90 A5 A61 I ST CAN2 bus receive pin
C2TX 21 89 E6 B50 O — CAN2 bus transmit pin
AC2RX — 8 E2 A6 1 ST Alternate CAN2 bus receive pin
AC2TX — 7 E4 B4 O — Alternate CAN2 bus transmit pin
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
(1)
Pin
Type
Buffer
Type
Description
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
TFBGA
124-pin
VTLA
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.