Datasheet

PIC32MX5XX/6XX/7XX
DS60001156H-page 324  2009-2013 Microchip Technology Inc.
REGISTER 24-33: EMAC1MADR: ETHERNET CONTROLLER MAC MII MANAGEMENT ADDRESS
REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
— — — PHYADDR<4:0>
7:0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — REGADDR<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-13 Unimplemented: Read as ’0’
bit 12-8 PHYADDR<4:0>: MII Management PHY Address bits
This field represents the 5-bit PHY Address field of Management cycles. Up to 31 PHYs can be addressed
(0 is reserved).
bit 7-5 Unimplemented: Read as ’0’
bit 4-0 REGADDR<4:0>: MII Management Register Address bits
This field represents the 5-bit Register Address field of Management cycles. Up to 32 registers can be
accessed.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.