Datasheet

PIC32MX5XX/6XX/7XX
DS60001156H-page 320  2009-2013 Microchip Technology Inc.
REGISTER 24-29: EMAC1SUPP: ETHERNET CONTROLLER MAC PHY SUPPORT REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
— — — — RESETRMII
(1)
— — SPEEDRMII
(1)
7:0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-12 Unimplemented: Read as ‘0’
bit 11 RESETRMII: Reset RMII Logic bit
(1)
1 = Reset the MAC RMII module
0 = Normal operation.
bit 10-9 Unimplemented: Read as ‘0’
bit 8 SPEEDRMII: RMII Speed bit
(1)
This bit configures the Reduced MII logic for the current operating speed.
1 = RMII is running at 100 Mbps
0 = RMII is running at 10 Mbps
bit 7-0 Unimplemented: Read as ‘0’
Note 1: This bit is only used for the RMII module.
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.