Datasheet

 2009-2013 Microchip Technology Inc. DS60001156H-page 305
PIC32MX5XX/6XX/7XX
bit 5 RXBUSY: Receive Busy bit
(2)
1 = RX logic is receiving data
0 = RX logic is idle
This bit indicates that a packet is currently being received. A change in this status bit is not necessarily
reflected by the RXDONE interrupt, as RX packets may be aborted or rejected by the RX filter.
bit 4-0 Unimplemented: Read as ‘0’
REGISTER 24-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER (CONTINUED)
Note 1: This bit will be set when the ON bit (ETHCON1<15>) = 1.
2: This bit will be cleared when the ON bit (ETHCON1<15>) = 0.