Datasheet

PIC32MX5XX/6XX/7XX
DS60001156H-page 302  2009-2013 Microchip Technology Inc.
REGISTER 24-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
— TXBUSE RXBUSE — — —EWMARKFWMARK
7:0
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
RXDONE PKTPEND RXACT — TXDONE TXABORT RXBUFNA RXOVFLW
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14 TXBUSE: Transmit BVCI Bus Error Interrupt bit
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
This bit is set when the TX DMA encounters a BVCI Bus error during a memory access. It is cleared by
either a Reset or CPU write of a ‘1’ to the CLR register.
bit 13 RXBUSE: Receive BVCI Bus Error Interrupt bit
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
This bit is set when the RX DMA encounters a BVCI Bus error during a memory access. It is cleared by
either a Reset or CPU write of a ‘1’ to the CLR register.
bit 12-10 Unimplemented: Read as ‘0’
bit 9 EWMARK: Empty Watermark Interrupt bit
1 = Empty Watermark pointer reached
0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is less than or equal to the value in the
RXEWM bit (ETHRXWM<0:7>) value. It is cleared by BUFCNT bit (ETHSTAT<16:23>)
being incremented by hardware. Writing a ‘0’ or a ‘1’ has no effect.
bit 8 FWMARK: Full Watermark Interrupt bit
1 = Full Watermark pointer reached
0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is greater than or equal to the value in the RXFWM
bit (ETHRXWM<16:23>) field. It is cleared by writing the BUFCDEC (ETHCON1<0>) bit to decrement
the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
bit 7 RXDONE: Receive Done Interrupt bit
1 = RX packet was successfully received
0 = No interrupt pending
This bit is set whenever an RX packet is successfully received. It is cleared by either a Reset or CPU
write of a ‘1’ to the CLR register.
Note: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.