Datasheet
2009-2013 Microchip Technology Inc. DS60001156H-page 301
PIC32MX5XX/6XX/7XX
REGISTER 24-13: ETHIEN: ETHERNET CONTROLLER INTERRUPT ENABLE REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
— TXBUSEIE
(1)
RXBUSEIE
(2)
— — — EWMARKIE
(2)
FWMARKIE
(2)
7:0
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
RXDONEIE
(2)
PKTPENDIE
(2)
RXACTIE
(2)
— TXDONEIE
(1)
TXABORTIE
(1)
RXBUFNAIE
(2)
RXOVFLWIE
(2)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-15 Unimplemented: Read as ‘0’
bit 14 TXBUSEIE: Transmit BVCI Bus Error Interrupt Enable bit
(1)
1 = Enable TXBUS Error Interrupt
0 = Disable TXBUS Error Interrupt
bit 13 RXBUSEIE: Receive BVCI Bus Error Interrupt Enable bit
(2)
1 = Enable RXBUS Error Interrupt
0 = Disable RXBUS Error Interrupt
bit 12-10 Unimplemented: Read as ‘0’
bit 9 EWMARKIE: Empty Watermark Interrupt Enable bit
(2)
1 = Enable EWMARK Interrupt
0 = Disable EWMARK Interrupt
bit 8 FWMARKIE: Full Watermark Interrupt Enable bit
(2)
1 = Enable FWMARK Interrupt
0 = Disable FWMARK Interrupt
bit 7 RXDONEIE: Receiver Done Interrupt Enable bit
(2)
1 = Enable RXDONE Interrupt
0 = Disable RXDONE Interrupt
bit 6 PKTPENDIE: Packet Pending Interrupt Enable bit
(2)
1 = Enable PKTPEND Interrupt
0 = Disable PKTPEND Interrupt
bit 5 RXACTIE: RX Activity Interrupt Enable bit
1 = Enable RXACT Interrupt
0 = Disable RXACT Interrupt
bit 4 Unimplemented: Read as ‘0’
bit 3 TXDONEIE: Transmitter Done Interrupt Enable bit
(1)
1 = Enable TXDONE Interrupt
0 = Disable TXDONE Interrupt
bit 2 TXABORTIE: Transmitter Abort Interrupt Enable bit
(1)
1 = Enable TXABORT Interrupt
0 = Disable TXABORT Interrupt
bit 1 RXBUFNAIE: Receive Buffer Not Available Interrupt Enable bit
(2)
1 = Enable RXBUFNA Interrupt
0 = Disable RXBUFNA Interrupt
bit 0 RXOVFLWIE: Receive FIFO Overflow Interrupt Enable bit
(2)
1 = Enable RXOVFLW Interrupt
0 = Disable RXOVFLW Interrupt
Note 1: This bit is only used for TX operations.
2: This bit is only used for RX operations.