Datasheet

 2009-2013 Microchip Technology Inc. DS60001156H-page 291
PIC32MX5XX/6XX/7XX
24.1 Control Registers
REGISTER 24-1: ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1
Bit Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTV<15:8>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PTV<7:0>
15:8
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
ON —SIDL— — — TXRTS RXEN
(1)
7:0
R/W-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0
AUTOFC — —MANFC— — — BUFCDEC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-16 PTV<15:0>: PAUSE Timer Value bits
PAUSE Timer Value used for Flow Control.
This register should only be written when RXEN (ETHCON1<8>) is not set.
These bits are only used for Flow Control operations.
bit 15 ON: Ethernet ON bit
1 = Ethernet module is enabled
0 = Ethernet module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Ethernet Stop in Idle Mode bit
1 = Ethernet module transfers are paused during Idle mode
0 = Ethernet module transfers continue during Idle mode
bit 12-10 Unimplemented: Read as ‘0’
bit 9 TXRTS: Transmit Request to Send bit
1 = Activate the TX logic and send the packet(s) defined in the TX EDT
0 = Stop transmit (when cleared by software) or transmit done (when cleared by hardware)
After the bit is written with a ‘1’, it will clear to a ‘0’ whenever the transmit logic has finished transmitting
the requested packets in the Ethernet Descriptor Table (EDT). If a ‘0’ is written by the CPU, the transmit
logic finishes the current packet’s transmission and then stops any further.
This bit only affects TX operations.
bit 8 RXEN: Receive Enable bit
(1)
1 = Enable RX logic, packets are received and stored in the RX buffer as controlled by the filter
configuration
0 = Disable RX logic, no packets are received in the RX buffer
This bit only affects RX operations.
Note 1: It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The
Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.