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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 100 (14x14) 32-Bit 80 MHz I/O number 85
281282283284285286287288289290
PIC32MX5XX/6XX/7XX
DS60001156H-page 288 2009-2013 Microchip Technology Inc.
REGISTER 23-22: CiFIFOUAn: CAN FIFO USER ADDRESS REGISTER ‘n’ (n = 0 THROUGH 31)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R-x R-x R-x R-x R-x R-x R-x R-x
CiFIFOUAn<31:24>
23:16
R-x R-x R-x R-x R-x R-x R-x R-x
CiFIFOUAn<23:16>
15:8
R-x R-x R-x R-x R-x R-x R-x R-x
CiFIFOUAn<15:8>
7:0
R-x R-x R-x R-x R-x R-x R-0
(1)
R-0
(1)
CiFIFOUAn<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CiFIFOUAn<31:0>: CAN FIFO User Address bits
TXEN =
1: (FIFO configured as a transmit buffer)
A read of this register will return the address where the next message is to be written (FIFO head).
TXEN =
0: (FIFO configured as a receive buffer)
A read of this register will return the address where the next message is to be read (FIFO tail).
Note 1: This bit will always read ‘0’, which forces byte-alignment of messages.
Note: This register is not guaranteed to read correctly in Configuration mode, and should only be accessed when
the module is not in Configuration mode.
REGISTER 23-23: CiFIFOCIN: CAN MODULE MESSAGE INDEX REGISTER ‘n’ (n = 0 THROUGH 31)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0U-0U-0U-0U-0U-0U-0U-0
— — — — — — — —
23:16
U-0U-0U-0U-0U-0U-0U-0U-0
— — — — — — — —
15:8
U-0U-0U-0U-0U-0U-0U-0U-0
— — — — — — — —
7:0
U-0U-0U-0R-0R-0R-0R-0R-0
— — — CiFIFOCI<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-5 Unimplemented: Read as ‘0’
bit 4-0 CiFIFOCIn<4:0>: CAN Side FIFO Message Index bits
TXEN =
1: (FIFO configured as a transmit buffer)
A read of this register will return an index to the message that the FIFO will next attempt to transmit.
TXEN =
0: (FIFO configured as a receive buffer)
A read of this register will return an index to the message that the FIFO will use to save the next message.