Datasheet

 2009-2013 Microchip Technology Inc. DS60001156H-page 287
PIC32MX5XX/6XX/7XX
bit 9 TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit
(1)
TXEN = 1: (FIFO configured as a transmit buffer)
1 = FIFO is  half full
0 = FIFO is > half full
TXEN =
0: (FIFO configured as a receive buffer)
Unused, reads ‘0’
bit 8 TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit
(1)
TXEN = 1: (FIFO configured as a transmit buffer)
1 = FIFO is empty
0 = FIFO is not empty, at least 1 message queued to be transmitted
TXEN =
0: (FIFO configured as a receive buffer)
Unused, reads ‘0’
bit 7-4 Unimplemented: Read as ‘0’
bit 3 RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit
TXEN =
1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN =
0: (FIFO configured as a receive buffer)
1 = Overflow event has occurred
0 = No overflow event occured
bit 2 RXFULLIF: Receive FIFO Full Interrupt Flag bit
(1)
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN =
0: (FIFO configured as a receive buffer)
1 = FIFO is full
0 = FIFO is not full
bit 1 RXHALFIF: Receive FIFO Half Full Interrupt Flag bit
(1)
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN =
0: (FIFO configured as a receive buffer)
1 = FIFO is half full
0 = FIFO is < half full
bit 0 RXNEMPTYIF: Receive Buffer Not Empty Interrupt Flag bit
(1)
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN =
0: (FIFO configured as a receive buffer)
1 = FIFO is not empty, has at least 1 message
0 = FIFO is empty
REGISTER 23-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (n = 0 THROUGH 31)
Note 1: This bit is read-only and reflects the status of the FIFO.