Datasheet

PIC32MX5XX/6XX/7XX
DS60001156H-page 286  2009-2013 Microchip Technology Inc.
REGISTER 23-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (n = 0 THROUGH 31)
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — TXNFULLIE TXHALFIE TXEMPTYIE
23:16
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE
15:8
U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
— — — — — TXNFULLIF
(1)
TXHALFIF TXEMPTYIF
(1)
7:0
U-0 U-0 U-0 U-0 R/W-0 R-0 R-0 R-0
— — — — RXOVFLIF RXFULLIF
(1)
RXHALFIF
(1)
RXNEMPTYIF
(1)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-27 Unimplemented: Read as ‘0’
bit 26 TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit
1 = Interrupt enabled for FIFO not full
0 = Interrupt disabled for FIFO not full
bit 25 TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 24 TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO empty
0 = Interrupt disabled for FIFO empty
bit 23-20 Unimplemented: Read as ‘0’
bit 19 RXOVFLIE: Overflow Interrupt Enable bit
1 = Interrupt enabled for overflow event
0 = Interrupt disabled for overflow event
bit 18 RXFULLIE: Full Interrupt Enable bit
1 = Interrupt enabled for FIFO full
0 = Interrupt disabled for FIFO full
bit 17 RXHALFIE: FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 16 RXNEMPTYIE: Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO not empty
0 = Interrupt disabled for FIFO not empty
bit 15-11 Unimplemented: Read as ‘0’
bit 10 TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit
(1)
TXEN = 1: (FIFO configured as a transmit buffer)
1 = FIFO is not full
0 = FIFO is full
TXEN =
0: (FIFO configured as a receive buffer)
Unused, reads ‘0’
Note 1: This bit is read-only and reflects the status of the FIFO.