Datasheet

 2009-2013 Microchip Technology Inc. DS60001156H-page 283
PIC32MX5XX/6XX/7XX
REGISTER 23-19: CiFIFOBA: CAN MESSAGE BUFFER BASE ADDRESS REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CiFIFOBA<31:24>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CiFIFOBA<23:16>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CiFIFOBA<15:8>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0
(1)
R-0
(1)
CiFIFOBA<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CiFIFOBA<31:0>: CAN FIFO Base Address bits
These bits define the base address of all message buffers. Individual message buffers are located based
on the size of the previous message buffers. This address is a physical address. Bits <1:0> are read-only
and read as ‘0’, forcing the messages to be 32-bit word-aligned in device RAM.
Note 1: This bit is unimplemented and will always read ‘0’, which forces word-alignment of messages.
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).