Datasheet

 2009-2013 Microchip Technology Inc. DS60001156H-page 269
PIC32MX5XX/6XX/7XX
bit 15 FLTEN5: Filter 17 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL5<1:0>: Filter 5 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL5<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
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00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN4: Filter 4 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL4<1:0>: Filter 4 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL4<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
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00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
REGISTER 23-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 (CONTINUED)
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.