Datasheet

PIC32MX5XX/6XX/7XX
DS60001156H-page 268  2009-2013 Microchip Technology Inc.
REGISTER 23-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN7 MSEL7<1:0> FSEL7<4:0>
23:16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN6 MSEL6<1:0> FSEL6<4:0>
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN5 MSEL5<1:0> FSEL5<4:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTEN4 MSEL4<1:0> FSEL4<4:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 FLTEN7: Filter 7 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL7<1:0>: Filter 7 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL7<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN6: Filter 6 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL6<1:0>: Filter 6 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL6<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.