Datasheet

PIC32MX5XX/6XX/7XX
DS60001156H-page 258  2009-2013 Microchip Technology Inc.
REGISTER 23-2: CiCFG: CAN BAUD RATE CONFIGURATION REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— WAKFIL — — — SEG2PH<2:0>
(1,4)
15:8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEG2PHTS
(1)
SAM
(2)
SEG1PH<2:0> PRSEG<2:0>
7:0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SJW<1:0>
(3)
BRP<5:0>
Legend: HC = Hardware Clear S = Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-23 Unimplemented: Read as ‘0’
bit 22 WAKFIL: CAN Bus Line Filter Enable bit
1 = Use CAN bus line filter for wake-up
0 = CAN bus line filter is not used for wake-up
bit 21-19 Unimplemented: Read as ‘0’
bit 18-16 SEG2PH<2:0>: Phase Buffer Segment 2 bits
(1,4)
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x T
Q
bit 15 SEG2PHTS: Phase Segment 2 Time Select bit
(1)
1 = Freely programmable
0 = Maximum of SEG1PH or Information Processing Time, whichever is greater
bit 14 SAM: Sample of the CAN Bus Line bit
(2)
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 13-11 SEG1PH<2:0>: Phase Buffer Segment 1 bits
(4)
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x T
Q
Note 1: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.
2: 3 Time bit sampling is not allowed for BRP < 2.
3: SJW  SEG2PH.
4: The Time Quanta per bit must be greater than 7 (that is, T
QBIT > 7).
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).