Datasheet

 2009-2013 Microchip Technology Inc. DS60001156H-page 239
PIC32MX5XX/6XX/7XX
bit 3 RTCWREN: RTC Value Registers Write Enable bit
(4)
1 = RTC Value registers can be written to by the user
0 = RTC Value registers are locked out from being written to by the user
bit 2 RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data
read. If the register is read twice and results in the same data, the data can be assumed to be valid.
0 = RTC Value registers can be read without concern about a rollover ripple
bit 1 HALFSEC: Half-Second Status bit
(5)
1 = Second half period of a second
0 = First half period of a second
bit 0 RTCOE: RTCC Output Enable bit
1 = RTCC clock output is enabled (clock presented onto an I/O)
0 = RTCC clock output is disabled
REGISTER 21-1: RTCCON: RTC CONTROL REGISTER (CONTINUED)
Note 1: The ON bit is only writable when RTCWREN = 1.
2: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
3: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
4: The RTCWREN bit can only be set when the write sequence is enabled.
5: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
Note: This register is only reset on a Power-on Reset (POR).