Datasheet

PIC32MX5XX/6XX/7XX
DS60001156H-page 222  2009-2013 Microchip Technology Inc.
bit 5 D_A: Data/Address bit (when operating as I
2
C slave)
This bit is cleared by hardware upon a device address match, and is set by hardware by reception of the
slave byte.
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
bit 4 P: Stop bit
This bit is set or cleared by hardware when a Start, Repeated Start, or Stop condition is detected.
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3 S: Start bit
This bit is set or cleared by hardware when a Start, Repeated Start, or Stop condition is detected.
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
bit 2 R_W: Read/Write Information bit (when operating as I
2
C slave)
This bit is set or cleared by hardware after reception of an I
2
C device address byte.
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
bit 1 RBF: Receive Buffer Full Status bit
This bit is set by hardware when the I2CxRCV register is written with a received byte, and is cleared by
hardware when software reads I2CxRCV.
1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
bit 0 TBF: Transmit Buffer Full Status bit
This bit is set by hardware when software writes to the I2CxTRN register, and is cleared by hardware upon
completion of data transmission.
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
REGISTER 18-2: I2CXSTAT: I
2
C™ STATUS REGISTER (CONTINUED)