Datasheet

 2009-2013 Microchip Technology Inc. DS60001156H-page 221
PIC32MX5XX/6XX/7XX
REGISTER 18-2: I2CXSTAT: I
2
C™ STATUS REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC
ACKSTAT TRSTAT — — — BCL GCSTAT ADD10
7:0
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC
IWCOL I2COV D_A P S R_W RBF TBF
Legend: HS = Set by hardware HSC = Hardware set/cleared
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared C = Clearable bit
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ACKSTAT: Acknowledge Status bit (when operating as I
2
C master, applicable to master transmit operation)
This bit is set or cleared by hardware at the end of a slave Acknowledge.
1 = NACK received from slave
0 = ACK received from slave
bit 14 TRSTAT: Transmit Status bit (when operating as I
2
C master, applicable to master transmit operation)
This bit is set by hardware at the beginning of a master transmission, and is cleared by hardware at the end
of a slave Acknowledge.
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
bit 13-11 Unimplemented: Read as ‘0’
bit 10 BCL: Master Bus Collision Detect bit
This bit is set by hardware at the detection of a bus collision.
1 = A bus collision has been detected during a master operation
0 = No collision
bit 9 GCSTAT: General Call Status bit
This bit is set by hardware when the address matches the general call address, and is cleared by hardware
clear at a Stop detection.
1 = General call address was received
0 = General call address was not received
bit 8 ADD10: 10-bit Address Status bit
This bit is set by hardware upon a match of the 2nd byte of the matched 10-bit address, and is cleared by
hardware at a Stop detection.
1 = 10-bit address was matched
0 = 10-bit address was not matched
bit 7 IWCOL: Write Collision Detect bit
This bit is set by hardware at the occurrence of a write to I2CxTRN while busy (cleared by software).
1 = An attempt to write the I2CxTRN register failed because the I
2
C module is busy
0 = No collision
bit 6 I2COV: Receive Overflow Flag bit
This bit is set by hardware at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow