Datasheet

PIC32MX5XX/6XX/7XX
DS60001156H-page 192  2009-2013 Microchip Technology Inc.
REGISTER 11-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
15:8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
7:0
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-8 Unimplemented: Read as ‘0’
bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)
1 = Direct connection to a low-speed device enabled
0 = Direct connection to a low-speed device disabled; hub required with PRE_PID
bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only)
1 = Retry NACK’d transactions disabled
0 = Retry NACK’d transactions enabled; retry done in hardware
bit 5 Unimplemented: Read as ‘0’
bit 4 EPCONDIS: Bidirectional Endpoint Control bit
If EPTXEN =
1 and EPRXEN = 1:
1 = Disable Endpoint ‘n’ from control transfers; only TX and RX transfers are allowed
0 = Enable Endpoint ‘n’ for control (SETUP) transfers; TX and RX transfers are also allowed
Otherwise, this bit is ignored.
bit 3 EPRXEN: Endpoint Receive Enable bit
1 = Endpoint ’n’ receive enabled
0 = Endpoint ’n’ receive disabled
bit 2 EPTXEN: Endpoint Transmit Enable bit
1 = Endpoint ’n’ transmit enabled
0 = Endpoint ’n’ transmit disabled
bit 1 EPSTALL: Endpoint Stall Status bit
1 = Endpoint ’n’ was stalled
0 = Endpoint ’n’ was not stalled
bit 0 EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint Handshake enabled
0 = Endpoint Handshake disabled (typically used for isochronous endpoints)