Datasheet

 2009-2013 Microchip Technology Inc. DS60001156H-page 153
PIC32MX5XX/6XX/7XX
REGISTER 9-8: CHEW3: CACHE WORD 3
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW3<31:24>
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW3<23:16>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW3<15:8>
7:0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW3<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEW3<31:0>: Word 3 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code-protected.
Note: This register is a window into the cache data array and is only readable if the device is not code-protected.
REGISTER 9-9: CHELRU: CACHE LRU REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0
— — — — — — — CHELRU<24>
23:16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CHELRU<23:16>
15:8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CHELRU<15:8>
7:0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
CHELRU<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-25 Unimplemented: Write ‘0’; ignore read
bit 24-0 CHELRU<24:0>: Cache Least Recently Used State Encoding bits
Indicates the pseudo-LRU state of the cache.