Datasheet

PIC32MX5XX/6XX/7XX
DS60001156H-page 152  2009-2013 Microchip Technology Inc.
REGISTER 9-6: CHEW1: CACHE WORD 1
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW1<31:24>
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW1<23:16>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW1<15:8>
7:0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW1<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEW1<31:0>: Word 1 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code-protected.
REGISTER 9-7: CHEW2: CACHE WORD 2
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW2<31:24>
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW2<23:16>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW2<15:8>
7:0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
CHEW2<7:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-0 CHEW2<31:0>: Word 2 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code-protected.