Datasheet

PIC32MX5XX/6XX/7XX
DS60001156H-page 150  2009-2013 Microchip Technology Inc.
REGISTER 9-3: CHETAG: CACHE TAG REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
LTAGBOOT — — — — — — —
23:16
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
LTAG<19:12>
15:8
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
LTAG<11:4>
7:0
R/W-x R/W-x R/W-x R/W-x R/W-0 R/W-0 R/W-1 U-0
LTAG<3:0> LVALID LLOCK LTYPE —
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31 LTAGBOOT: Line Tag Address Boot bit
1 = The line is in the 0x1D000000 (physical) area of memory
0 = The line is in the 0x1FC00000 (physical) area of memory
bit 30-24 Unimplemented: Write ‘0’; ignore read
bit 23-4 LTAG<19:0>: Line Tag Address bits
LTAG<19:0> bits are compared against physical address to determine a hit. Because its address range and
position of PFM in kernel space and user space, the LTAG PFM address is identical for virtual addresses,
(system) physical addresses, and PFM physical addresses.
bit 3 LVALID: Line Valid bit
1 = The line is valid and is compared to the physical address for hit detection
0 = The line is not valid and is not compared to the physical address for hit detection
bit 2 LLOCK: Line Lock bit
1 = The line is locked and will not be replaced
0 = The line is not locked and can be replaced
bit 1 LTYPE: Line Type bit
1 = The line caches instruction words
0 = The line caches data words
bit 0 Unimplemented: Write ‘0’; ignore read