Datasheet

PIC32MX5XX/6XX/7XX
DS60001156H-page 148  2009-2013 Microchip Technology Inc.
9.2 Control Registers
REGISTER 9-1: CHECON: CACHE CONTROL REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
23:16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CHECOH
15:8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — DCSZ<1:0>
7:0
U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
— — PREFEN<1:0> —PFMWS<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 31-17 Unimplemented: Write ‘0’; ignore read
bit 16 CHECOH: Cache Coherency Setting on a PFM Program Cycle bit
1 = Invalidate all data and instruction lines
0 = Invalidate all data lnes and instruction lines that are not locked
bit 15-10 Unimplemented: Write ‘0’; ignore read
bit 9-8 DCSZ<1:0>: Data Cache Size in Lines bits
Changing these bits causes all lines to be reinitialized to the “invalid” state.
11 = Enable data caching with a size of 4 lines
10 = Enable data caching with a size of 2 lines
01 = Enable data caching with a size of 1 line
00 = Disable data caching
bit 7-6 Unimplemented: Write ‘0’; ignore read
bit 5-4 PREFEN<1:0>: Predictive Prefetch Enable bits
11 = Enable predictive prefetch for both cacheable and non-cacheable regions
10 = Enable predictive prefetch only for non-cacheable regions
01 = Enable predictive prefetch only for cacheable regions
00 = Disable predictive prefetch
bit 3 Unimplemented: Write ‘0’; ignore read
bit 2-0 PFMWS<2:0>: PFM Access Time Defined in Terms of SYSLK Wait States bits
111 = Seven Wait states
110 = Six Wait states
101 = Five Wait states
100 = Four Wait states
011 = Three Wait states
010 = Two Wait states
001 = One Wait state
000 = Zero Wait state