PIC32MX5XX/6XX/7XX 32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM) with Graphics Interface, USB, CAN, and Ethernet Operating Conditions Timers/Output Compare/Input Capture • 2.3V to 3.
PIC32MX5XX/6XX/7XX TABLE 1: PIC32 USB AND CAN – FEATURES Program Memory (KB) Data Memory (KB) USB CAN Timers/Capture/Compare DMA Channels (Programmable/Dedicated) UART(2,3) SPI(3) I2C™(3) 10-bit 1 Msps ADC (Channels) Comparators PMP/PSP JTAG Trace Packages(4) PIC32MX534F064H 64 64 + 12(1) 16 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX564F064H 64 64 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX564F128H 64 128 + 12(1) 32 1 1 5/5/5
PIC32MX5XX/6XX/7XX TABLE 2: PIC32 USB AND ETHERNET – FEATURES Program Memory (KB) Data Memory (KB) USB Ethernet Timers/Capture/Compare DMA Channels (Programmable/Dedicated) UART(2,3) SPI(3) I2C™(3) 10-bit 1 Msps ADC (Channels) Comparators PMP/PSP JTAG Trace Packages(4) PIC32MX664F064H 64 64 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX664F128H 64 128 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No PT, MR PIC32MX675F256H 64 256 + 12(1) 64
PIC32MX5XX/6XX/7XX TABLE 3: PIC32 USB, ETHERNET AND CAN – FEATURES Pins Program Memory (KB) Data Memory (KB) USB Ethernet CAN Timers/Capture/Compare DMA Channels (Programmable/Dedicated) UART(2,3) SPI(3) I2C™(3) 10-bit 1 Msps ADC (Channels) Comparators JTAG Trace Packages(4) PIC32MX764F128H 64 128 + 12(1) 32 1 1 1 5/5/5 4/8 6 3 4 16 2 Yes Yes No PT, MR PIC32MX775F256H 64 256 + 12(1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No PT, MR PIC32MX775F512H 64 512 +
PIC32MX5XX/6XX/7XX Pin Diagrams 64-Pin QFN(1) PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 C1TX/RF1 C1RX/RF0 VDD VCAP CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 SCK3/U4TX/U1RTS/OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN(1) ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0 VDD VCAP ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMR
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN(1) ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 PIC32MX775F256H 8 40 PIC32MX775F512H 9 39 PIC32MX795F512H 10 38 11 37 12 36 13 35 1
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN(1) ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 PIC32MX764F128H 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) = Pins are up to 5V tolerant PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 C1TX/RF1 C1RX/RF0 VDD VCAP CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 SCK3/U4TX/U1RTS/OC2/RD1 64-Pin TQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0 VDD VCAP ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 ERXERR/PMD4/RE4 ERXCLK/EREFCLK/PMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 PIC32MX775F256H 9 PIC32MX775F512H 10 PIC32MX795F512H 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 EC
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 PIC32MX764F128H 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC32MX534F064L PIC32MX564F064L PIC32MX564F128L PIC32MX575F512L PIC32MX575F256L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/IC1/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 ETXERR/PMD9/RG1 ETXD0/PMD10/RF1 ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 PIC32MX664F064L PIC32MX664F128L PIC32MX675F256L PIC32MX675F512L PIC32MX695F512L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PIC32MX775F256L PIC32MX775F512L PIC32MX795F512L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DS60001156H-page 15 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 VSS VDD TCK/RA1 AC1TX/SCK4/U5TX/U2RTS/RF13 AC1RX/SS4/U5RX/U2CTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ER
PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 ETXERR/PMD9/RG1 C1TX/ETXD0/PMD10/RF1 C1RX/ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 PIC32MX764F128L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 1
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 121-Pin TFBGA(1) = Pins are up to 5V tolerant PIC32MX534F064L PIC32MX564F064L PIC32MX664F064L PIC32MX564F128L PIC32MX664F128L PIC32MX764F128L PIC32MX575F256L PIC32MX675F256L PIC32MX775F256L PIC32MX575F512L PIC32MX675F512L PIC32MX695F512L PIC32MX775F512L PIC32MX795F512L 1 2 3 4 5 6 7 8 9 10 11 RE4 RE3 RG13 RE0 RG0 RF1 VDD VSS RD12 RD2 RD1 NC RG15 RE2 RE1 RA7 RF0 VCAP RD5 RD3 VSS RC14 RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD R
PIC32MX5XX/6XX/7XX TABLE 4: PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L AND PIC32MX575F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 SCL1/INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 C1TX/PMD10/RF1 F2 SCL4/SDO2/U3TX/PMA3/CN10/RG8 A7 VDD F3 SS2/U6RX/U3CTS/PMA2/CN11/RG9 A8 VSS F4 SDA4/SDI2/U3RX/PMA4/CN9/RG7 A9 IC5/PMD12/RD12 F5 V
PIC32MX5XX/6XX/7XX TABLE 4: PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L AND PIC32MX575F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 AC1RX/SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS/RF13 K8 VDD L7 AN13/PMA10/RB13 K9 SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15 K10 USBID/RF3 L9 SS3/U
PIC32MX5XX/6XX/7XX TABLE 5: PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 A2 PMD3/RE3 E9 AETXEN/SDA1/INT4/RA15 RTCC/EMDIO/AEMDIO/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV//SCL4/SDO2/ U3TX/PMA3/CN10/RG8 A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6R
PIC32MX5XX/6XX/7XX TABLE 5: PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 K6 SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 SCK4/U5TX/U2RTS/RF13 K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13 K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN1
PIC32MX5XX/6XX/7XX TABLE 6: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14 A5 C2RX/PMD8/RG0 F1 MCLR A6 C1TX/ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/ U3TX/PMA3/CN10/RG8 A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/ U3CTS/PMA2/CN11/RG9
PIC32MX5XX/6XX/7XX TABLE 6: PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 K5 No Connect (NC) L4 AVSS AN9/C2OUT/RB9 K6 AC1RX/SS4/U5RX/U2CTS/RF12 L5 AN10/CVREFOUT/PMA13/RB10 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS/RF13 K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13 K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 AETXD0/SS3/U4RX/
PIC32MX5XX/6XX/7XX TABLE 7: PIN NAME: PIC32MX764F128L DEVICE Pin Number Full Pin Name Pin Number Full Pin Name A1 PMD4/RE4 E8 AETXEN/SDA1/INT4/RA15 A2 PMD3/RE3 E9 RTCC/EMDIO/AEMDIO/IC1/RD8 A3 TRD0/RG13 E10 SS1/IC2/RD9 A4 PMD0/RE0 E11 AETXCLK/SCL1/INT3/RA14 A5 PMD8/RG0 F1 MCLR A6 C1TX/ETXD0/PMD10/RF1 F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/ U3TX/PMA3/CN10/RG8 A7 VDD F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/ U3CTS/PMA2/CN11/RG9 A8 VSS F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG
PIC32MX5XX/6XX/7XX TABLE 7: PIN NAME: PIC32MX764F128L DEVICE (CONTINUED) Pin Number Full Pin Name Pin Number Full Pin Name K4 AN8/C1OUT/RB8 L3 AVSS K5 No Connect (NC) L4 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 K6 AC1RX/SS4/U5RX/U2CTS/RF12 L5 K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 L6 AC1TX/SCK4/U5TX/U2RTS/RF13 K8 VDD L7 AN13/ERXD1/AECOL/PMA10/RB13 K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 K10 USBID/RF3 L9 AETXD0/SS3/U4RX/U1CTS/CN20/RD14 K
PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 124-Pin VTLA(1) A68 A67 A1 = Pins are up to 5V tolerant A66 A65 A64 A63 A62 A61 A60 A59 A58 A57 A56 A55 A54 A53 A52 A51 B56 B55 B54 B53 B52 B51 B50 B49 B48 B47 B46 B45 B44 B43 B42 A50 A2 B1 A49 A3 B2 B41 A48 A4 B3 B40 A47 A5 B4 B39 A46 A6 B5 B38 A45 A7 B6 B37 A44 A8 B7 B36 A43 A9 B8 B35 A42 A10 B9 B34 A41 A11 B10 B33 A40 A12 B11 B32 A39 A13 B12 B31 A38 A14 B13 B30 A37 B29 A36
PIC32MX5XX/6XX/7XX TABLE 8: PIN NAMES: PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES Package Bump # Full Pin Name Package Bump # Full Pin Name A1 No Connect (NC) A52 OC2/RD1 A2 AERXERR/RG15 A53 OC4/RD3 A3 VSS A54 ETXD3/PMD13/CN19/RD13 A4 PMD6/RE6 A55 PMRD/CN14/RD5 A5 T2CK/RC1 A56 ETXCLK/PMD15/CN16/RD7 A6 T4CK/AC2RX(1)/RC3 A57 No Connect (NC) A7 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 A58 No Connect (NC) A8 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/ U3TX/PMA3/CN10/RG8
PIC32MX5XX/6XX/7XX TABLE 8: PIN NAMES: PIC32MX675F512L, PIC32MX695F512L, AND PIC32MX795F512L DEVICES Package Bump # Full Pin Name Package Bump # Full Pin Name B35 No Connect (NC) B46 VSS B36 AETXCLK/SCL1/INT3/RA14 B47 No Connect (NC) B37 RTCC/EMDIO/AEMDIO/IC1/RD8 B48 VCAP B38 SCK1/IC3/PMCS2/PMA15/RD10 B49 C1RX/ETXD1/PMD11/RF0 B39 SDO1/OC1/INT0/RD0 B50 C2TX/ETXERR/PMD9/RG1 B40 SOSCO/T1CK/CN0/RC14 B51 TRCLK/RA6 B41 VSS B52 PMD0/RE0 B42 OC3/RD2 B53 VDD B43 ETXD2/IC5/PMD12/R
PIC32MX5XX/6XX/7XX Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 33 2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 45 3.0 CPU.....................................................................................................
PIC32MX5XX/6XX/7XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC32MX5XX/6XX/7XX Referenced Sources This device data sheet is based on the following individual chapters of the “PIC32 Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note 1: To access the documents listed below, browse to the documentation section of the PIC32MX795F512L product page on the Microchip web site (www.microchip.com) or select a family reference manual section from the following list.
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 32 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 1.0 DEVICE OVERVIEW This document contains device-specific information for PIC32MX5XX/6XX/7XX devices. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number(1) Pin Name Pin Type Buffer Type Description 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA AN0 16 25 K2 B14 I Analog Analog input channels AN1 15 24 K1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 23 22 21 20 26 27 32 33 34 35 41 42 43 44 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 A15 B13 A13 B11 A12 A20 B16 A23 B19 A24 B20 B23 A28 B24 A29 I I I I I I
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 IC1 IC2 IC3 IC4 IC5 OCFA OC1 OC2 OC3 OC4 OC5 OCFB INT0 INT1 INT2 INT3 INT4 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 32 — — — 42 43 44 45 52 17 46 49 50 51 52 30 46 42 43 44 45 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 50 80 47 48 68 69 70
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA9 RA10 RA14 RA15 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 RC1 RC2 RC3 RC4 RC12 RC13 RC14 RC15 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA — — — — — — — — — — — — 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 — — — — 39 47 48 40 17 38 58 59 60 61 91 92 28 29 66 67 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 6 7 8 9 63 73 74 64 G3 J6
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 RF0 RF1 RF2 RF3 RF4 RF5 RF8 RF12 RF13 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA 46 49 50 51 52 53 54 55 42 43 44 45 — — — — 60 61 62 63 64 1 2 3 — — 58 59 — 33 31 32 — — — 72 76 77 78 81 82 83 84 68 69 70 71 79 80 47 48 93 94 98 99 100 3 4 5 18 19 87 88 52 51 49 50 53 40 39 D9 A11 A10 B9 C
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name Pin Type Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST PORTG is a bidirectional I/O port B50 A7 B6 A8 A9 A65 B55 B54 A2 B31 A38 B40 A5 B4 A6 B5 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I B26 I ST UART1 clear to send 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin TFBGA 124-pin VTLA RG0 RG1 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 RG2 RG3 T1CK T2CK T3CK T4CK T5CK — — 4 5 6 8 — — — — 37 36 48
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type B39 O — E10 A45 I/O ST 48 K9 A31 I/O ST 50 51 52 53 K11 J10 A36 B29 I O ST — SS3 43 47 L9 B26 I/O ST SCK2 4 10 E3 A7 I/O ST SDI2 SDO2 5 6 11 12 F4 F2 B6 A8 I O ST — SS2 8 14 F3 A9 I/O ST SCK4 29 39 L6 B22 I/O ST SDI4 SDO4 31 32 49 50 L10 L11 B27 A32 I O ST — SS4 21 40 K6 A27 I/O SCL1 44 66 E11 B36 SDA1 43 67 E8 A44 SCL3 51 53 J
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type B9 A26 A40 B33 B37 I I I O O ST ST ST — — A21 B17 A24 B11 A12 A23 B13 A13 B19 I I O I I O I I O Analog Analog Analog Analog Analog — Analog Analog — L8 A29 I/O 43 K7 B24 I/O 8 6 5 4 16 22 32 31 28 27 24 23 45 44 14 12 11 10 29 28 50 49 42 41 35 34 71 70 F3 F2 F4 E3 K3 L2 L11 L10 L7 J7 J5 L5 C11 D11 A9 A8 B6 A7 B17 A21 A32 B27 A28 B23 B20 A24 A46 B38 O O O O O O O O O O O O O O PMCS1 45
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type A64 A66 B56 A67 B2 A4 B3 A61 B50 A60 B49 B43 A54 B45 A56 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST L8 A29 O 43 K7 B24 O 53 52 34 82 81 54 B8 C8 H8 A55 B44 A37 O O I VUSB3V3 35 55 H9 B30 P VBUSON 11 20 H1 A12 O D+ DUSBID C1RX C1TX AC1RX AC1TX C2RX
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type B23 A28 B24 I I I ST ST ST Ethernet Receive Data 0(2) Ethernet Receive Data 1(2) Ethernet Receive Data 2(2) A29 B20 A8 A8 A9 A9 I I I I I I ST ST ST ST ST ST Ethernet Receive Data 3(2) Ethernet receive error input(2) Ethernet receive data valid(2) Ethernet carrier sense data valid(2) Ethernet receive clock(2) Ethernet reference clock(2) A6 B6 A9 D8 A60 B49 B43 A54 O O O O — — — — Ethernet Tran
PIC32MX5XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Type Buffer Type A46 O — E9 C5 B37 B51 I/O O — — 97 96 A3 C3 B55 A65 O O — — — — 95 92 C4 B5 B54 A62 O O — — PGED1 16 25 K2 B14 I/O ST PGEC1 15 24 K1 A15 I ST PGED2 18 27 J3 B16 I/O ST PGEC2 17 26 L1 A20 I ST MCLR 7 13 F1 B7 I/P ST AVDD 19 30 J4 A22 P P AVSS 20 31 L3 B18 P P A7, C2, C9, E5, K8, F8, G5, H4, H6 B7 A10, A14, A30, A41, A48, A59, B1, B21, B53
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 44 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX FIGURE 2-1: VDD 2.2 R1 MCLR C (1) PIC32MX VUSB3V3 The AVDD and AVSS pins must be connected, regardless of the ADC use and the ADC voltage reference source. Decoupling Capacitors The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A value of 0.1 µF (100 nF), 10-20V is recommended.
PIC32MX5XX/6XX/7XX 2.3 Capacitor on Internal Voltage Regulator (VCAP) 2.3.1 2.5 INTERNAL REGULATOR MODE A low-ESR (1 ohm) capacitor is required on the VCAP pin, which is used to stabilize the internal voltage regulator output. The VCAP pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 31.0 “Electrical Characteristics” for additional information on CEFC specifications. 2.
PIC32MX5XX/6XX/7XX 2.7 Trace 2.9 The trace pins can be connected to a hardware-traceenabled programmer to provide a compress real time instruction trace. When used for trace the TRD3, TRD2, TRD1, TRD0 and TRCLK pins should be dedicated for this use. The trace hardware requires a 22 series resistor between the trace pins and the trace connector. 2.
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 48 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 3.0 CPU Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS60001113) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32® M4K® Processor Core are available at http://www.mips.com.
PIC32MX5XX/6XX/7XX 3.2 Architecture Overview 3.2.2 The MIPS® M4K® processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: • • • • • • • • Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e® Support Enhanced JTAG (EJTAG) Controller 3.2.
PIC32MX5XX/6XX/7XX The MIPS® architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file. In addition to the HI/LO targeted operations, the MIPS32® architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair.
PIC32MX5XX/6XX/7XX Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority. TABLE 3-3: PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES Exception Description Reset Assertion MCLR or a Power-on Reset (POR). DSS EJTAG debug single step. DINT EJTAG debug interrupt.
PIC32MX5XX/6XX/7XX 3.3 Power Management ® ® The MIPS M4K Processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or halting the clocks, which reduces system power consumption during idle periods. 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking Power-Down mode is through execution of the WAIT instruction.
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 54 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. For detailed information, refer to Section 3. “Memory Organization” (DS60001115) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB of unified virtual memory address space.
PIC32MX5XX/6XX/7XX FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX564F064H, PIC32MX564F064L, PIC32MX664F064H AND PIC32MX664F064L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD010000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0008000 Reserved 0xA0007FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x
PIC32MX5XX/6XX/7XX FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX534F064H AND PIC32MX534F064L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD010000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0004000 Reserved 0xA0003FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x1FC03000 Device Config
PIC32MX5XX/6XX/7XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX564F128H, PIC32MX564F128L, PIC32MX664F128H, PIC32MX664F128L, PIC32MX764F128H AND PIC32MX764F128L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD020000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0008000 Reserved 0xA0007FFF RAM(2) 0
PIC32MX5XX/6XX/7XX FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L, PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND PIC32MX775F256L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD040000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0010000 Reserved 0xA000FFFF RAM(2) 0
PIC32MX5XX/6XX/7XX FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L, PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND PIC32MX775F512L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD080000 KSEG1 0xBF8FFFFF Reserved Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0010000 Reserved 0xA000FFFF RAM(2) 0
PIC32MX5XX/6XX/7XX FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L, PIC32MX795F512H AND PIC32MX795F512L DEVICES Virtual Memory Map(1) 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 Physical Memory Map(1) 0xFFFFFFFF Reserved Device Configuration Registers 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 Reserved SFRs 0xBF800000 0xBD080000 Reserved KSEG1 0xBF8FFFFF Reserved 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0020000 Reserved 0xA001FFFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x
Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 31:16 — — — — — BMXCHEDMA — — 15:0 — — — — — — — — 31:16 2010 BMXDKPBA(1) 15:0 — — — — — — — — 31:16 2020 BMXDUDBA(1) 15:0 — — — — — — — — 31:16 — 2030 BMXDUPBA(1) 2040 BMXDRMSZ 2060 BMXPFMSZ 2070 BMXBOOTSZ — — — — — — — 31:16 15:0 19/3 18/2 17/1 — — — — BMXWSDRM — 16/0 — — — — — — — — — — — — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F BMXARB<2:0>
Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND PIC32MX575F512H DEVICES 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 DS60001156H-page 63 1090 IPC0 10A0 IPC1 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — 15:0 — — — — — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — — — — — INT4EP
Virtual Address (BF88_#) Register Name(1) 10B0 IPC2 INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND PIC32MX575F512H DEVICES (CONTINUED) IPC3 10D0 IPC4 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 2009-2013 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name(1) 1000 INTCON 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 DS60001156H-page 65 1080 IEC2 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 Legend: 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — 15:0 — — — — — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — — — — — SS0 0000 — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 — — — — — — — — — — TPC<2:0> — — 31
Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 10E0 IPC5 INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES (CONTINUED) 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 15:0 — — — IC4IP<2:0> IC4IS<1:0>
Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 1080 IEC2 1090 IPC0 10A0 IPC1 DS60001156H-page 67 10B0 IPC2 IPC3 10C0 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — — — — — S
Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES (CONTINUED) 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 — — — INT4IP<2:0> 15:0 — — — IC4IP<2:0> 31:16 — — — 15:0 — — — IC5IP<2:0> 31:16 — — — AD1IP<2:0> 15:0 31:16 — — — — 28/12 — — 27/11 — 26/10 — I2C1IP<2:0> — 25/9 23/7 22/6
Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND PIC32MX575F256L DEVICES 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 DS60001156H-page 69 1080 IEC2 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — — — — — 15:0 — — — — — 25/9 24/8 23/7 22/6 21/5 — — — —
Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND PIC32MX575F256L DEVICES (CONTINUED) 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 — — — INT4IP<2:0> 15:0 — — — IC4IP<2:0> 31:16 — — — 15:0 — — 31:16 — — 15:0 31:16 — — — — 28/12 23/7 22/6 21/5 INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 IC4
Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 DS60001156H-page 71 1080 IEC2 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — 15:0 — — — — — — — — — 25/9 24/8 23/7 22/6 21/5 — — — —
Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES (CONTINUED) 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 — — — INT4IP<2:0> 15:0 — — — IC4IP<2:0> 31:16 — — — 15:0 — — 31:16 — — 15:0 31:16 — — — — 28/12 23/7 22/6 21/5 INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 IC
Virtual Address (BF88_#) Register Name(1) 1000 INTCON INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 1010 INTSTAT(3) 1020 IPTMR 1030 IFS0 1040 IFS1 1050 IFS2 IEC0 1070 IEC1 DS60001156H-page 73 1080 IEC2 1090 IPC0 10A0 IPC1 10B0 IPC2 10C0 IPC3 30/14 29/13 28/12 27/11 26/10 31:16 — — 15:0 — — — — — — — MVEC — 31:16 — 15:0 — — — — — — — — — 25/9 24/8 23/7 22/6 21/5 — — — — — — — — —
Virtual Address (BF88_#) Register Name(1) 10D0 IPC4 INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) 10E0 IPC5 10F0 IPC6 1100 IPC7 1110 IPC8 1120 IPC9 1130 IPC10 1140 IPC11 1150 IPC12 31/15 30/14 29/13 31:16 — — — INT4IP<2:0> 15:0 — — — IC4IP<2:0> 31:16 — — — 15:0 — — 31:16 — — 15:0 31:16 — — — — 23/7 22/6 21/5 INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000 IC4IS<1:0> — — — T4IP<
Virtual Address (BF80_#) TIMER1-TIMER5 REGISTER MAP 0600 T1CON 0610 TMR1 0620 PR1 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — 15:0 ON — SIDL 31:16 — — — — — — — — TWDIS TWIP — — — — — 15:0 31:16 0810 TMR2 0820 PR2 TMR3 0A20 PR3 0C20 PR4 TMR5 0E20 PR5 — — — — TCKPS<1:0> — — — — — — — — — — — — — — — — 31:16 — — — — — — — — — 15:0 ON — SIDL — — — — — TGATE 31:16 — — — — — — — — — 15:0 — — —
Virtual Address (BF80_#) Register Name 2000 IC1CON(1) 2010 IC1BUF 2200 IC2CON(1) 2210 IC2BUF 2400 IC3CON(1) 2410 IC3BUF 2600 IC4CON(1) 2610 IC4BUF 2800 IC5CON(1) 2810 IC5BUF INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 31:16 — 15:0 ON 25/9 — — — — — — — SIDL — — — FEDGE 31:16 24/8 23/7 22/6 21/5 — — — — C32 ICTMR 15:0 — — — — — — — — — 15:0 ON — SIDL — — — FEDGE C32 ICTMR 31:16 18/2 — — — ICO
Virtual Address (BF80_#) OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP 3000 OC1CON 3010 OC1R 3020 OC1RS 3200 OC2CON 3210 OC2R 3220 OC2RS 3400 OC3CON 3410 OC3R 3420 OC3RS 3610 OC4R 3620 OC4RS 3800 OC5CON 3810 OC5R 3820 OC5RS 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 — 15:0 ON — — — — — — — — — — — SIDL — — — — — — — OC32 31:16 21/5 20/4 19/3 18/2 — — — OCFLT OCTSEL 31:16 0000 xxxx xxxx — — — — — — — — — — — — 15:0
Virtual Address (BF80_#) Register Name(1) 2009-2013 Microchip Technology Inc.
Virtual Address (BF80_#) Register Name(1) 5220 I2C5ADD 5230 I2C5MSK 5240 I2C5BRG 5250 I2C5TRN 5260 I2C5RCV 5300 I2C1CON 5310 I2C1STAT 5320 I2C1ADD 5330 I2C1MSK 5340 I2C1BRG 5350 I2C1TRN 5360 I2C1RCV I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP (CONTINUED) All Resets Bits Bit Range 2009-2013 Microchip Technology Inc.
Virtual Address (BF80_#) 5410 I2C2STAT 5420 I2C2ADD 5430 I2C2MSK 5440 I2C2BRG I2C2TRN 5460 I2C2RCV 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name(1) Bits 5400 I2C2CON 5450 I2C2 REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX79
Virtual Address (BF80_#) UART1 THROUGH UART6 REGISTER MAP 6000 U1MODE(1) 6010 U1STA(1) 6020 U1TXREG 6030 U1RXREG 6040 U1BRG(1) 6200 U4MODE(1) U4STA(1) 6220 U4TXREG 6230 U4RXREG 6240 U4BRG(1) 6400 U3MODE(1) 6410 U3STA(1) 6420 U3TXREG 6430 U3RXREG 6440 U3BRG(1) DS60001156H-page 81 6600 U6MODE(1) 6610 U6STA(1) 6620 U6TXREG 30/14 29/13 31:16 — — — 15:0 ON — SIDL 31:16 — — 15:0 UTXISEL<1:0> 31:16 — 15:0 28/12 27/11 26/10 25/9 24/8 — — — — — IREN RTSMD —
Virtual Address (BF80_#) Register Name 6630 U6RXREG 6640 U6BRG(1) UART1 THROUGH UART6 REGISTER MAP (CONTINUED) 6800 U2MODE(1) U2STA(1) 6810 6820 U2TXREG 6830 U2RXREG 6840 U2BRG(1) 6A00 U5MODE(1) U5STA(1) 6A10 6A20 U5TXREG 6A30 U5RXREG 6A40 U5BRG(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — 15:0 — — — — — — — — — — — — RX8 31:16 — — — — — — — — 15:0 20/4 19/3 18/2 17/1 16/0 — — — — — Receive Register
Virtual Address (BF80_#) 5800 SPI3CON 5810 SPI3STAT 5820 SPI3BUF 5830 SPI3BRG 5A00 SPI2CON 5A10 SPI2STAT 5A20 SPI2BUF 5A30 SPI2BRG 5C00 SPI4CON SPI4BUF 5C30 SPI4BRG 30/14 29/13 31:16 FRMEN 15:0 ON FRMSYNC FRMPOL — SIDL 31:16 — — — 15:0 — — — 28/12 27/11 26/10 MSSEN FRMSYPW DISSDO MODE32 25/9 SMP — CKE SSEN — — — SRMT SPIROV SPIRBE RXBUFELM<4:0> — SPIBUSY — — SPITUR 22/6 21/5 20/4 19/3 18/2 17/1 — — CKP MSTEN — — — SPIFE — STXISEL<1:0> 16/0 ENHB
Virtual Address (BF80_#) 5E10 SPI1STAT SPI1BUF 5E30 SPI1BRG 31/15 30/14 29/13 31:16 FRMEN 15:0 ON FRMSYNC FRMPOL — SIDL 31:16 — — — 15:0 — — — 28/12 27/11 26/10 MSSEN FRMSYPW DISSDO MODE32 25/9 24/8 23/7 — CKE SSEN — — — SRMT SPIROV SPIRBE FRMCNT<2:0> MODE16 SMP RXBUFELM<4:0> — SPIBUSY — — 31:16 SPITUR 22/6 21/5 20/4 19/3 18/2 17/1 — — CKP MSTEN — — — SPIFE — STXISEL<1:0> 16/0 ENHBUF 0000 SRXISEL<1:0> TXBUFELM<4:0> — SPITBE — 31:16 — — —
Virtual Address (BF80_#) ADC REGISTER MAP 9000 AD1CON1(1) 9010 AD1CON2(1) 9020 AD1CON3(1) 9040 AD1CHS(1) 9060 AD1PCFG(1) 9050 AD1CSSL(1) 9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90B0 ADC1BUF4 90C0 ADC1BUF5 90D0 ADC1BUF6 90E0 ADC1BUF7 90F0 ADC1BUF8 DS60001156H-page 85 9100 ADC1BUF9 9110 ADC1BUFA 9120 ADC1BUFB 30/14 29/13 28/12 27/11 26/10 31:16 — 15:0 ON 31:16 — — — — — — SIDL — — — — — — — — — — — — 15:0 VCFG2 VCFG1 VCFG0 OFFCAL — CSCNA — — BUFS — 31:16 — —
Virtual Address (BF80_#) ADC REGISTER MAP (CONTINUED) 9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 9160 ADC1BUFF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ADC Result Word C (ADC1BUFC<31:0>) ADC Result Word D (ADC1BUFD<31:0>) ADC Result Word E (ADC1BUFE<31:0>) ADC Result Word F (ADC1BUFF<31:0>) Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Virtual Address (BF88_#) 3000 DMACON(1) DMASTAT 3020 DMAADDR 30/14 29/13 31:16 — — — 15:0 ON — — 31:16 — — — — 15:0 — — — — 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — — — — — — — — — — — — — — — — — — RDWR SUSPEND DMABUSY 31:16 DMACH<2:0>(2) 0000 DMAADDR<31:0> 15:0 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’.
Virtual Address (BF88_#) 3070 DCH0ECON 3090 DCH0INT DCH0SSA 30A0 DCH0DSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 30F0 DCH0CSIZ 3100 DCH0CPTR 3110 DCH0DAT 3120 DCH1CON 2009-2013 Microchip Technology Inc.
Virtual Address (BF88_#) 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON 3200 DCH2INT DCH2SSA 3220 DCH2DSA 3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR 3260 DCH2DPTR 3270 DCH2CSIZ DS60001156H-page 89 3280 DCH2CPTR 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — 15:0 31:16 — — — — — — — — — — — — — — 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — —
Virtual Address (BF88_#) Register Name(1) 3290 DCH2DAT 32B0 DCH3ECON DCH3INT 32D0 DCH3SSA 32E0 DCH3DSA 32F0 DCH3SSIZ 3300 DCH3DSIZ 3310 DCH3SPTR 3320 DCH3DPTR 3330 DCH3CSIZ 3340 DCH3CPTR 3350 DCH3DAT 2009-2013 Microchip Technology Inc.
Virtual Address (BF88_#) 33B0 DCH4SSIZ 33C0 DCH4DSIZ 33D0 DCH4SPTR 33E0 DCH4DPTR 33F0 DCH4CSIZ 3400 DCH4CPTR 3410 DCH4DAT 3420 DCH5CON 3430 DCH5ECON 3450 DCH5INT DCH5SSA 3460 DCH5DSA 3470 DCH5SSIZ 3480 DCH5DSIZ 3490 DCH5SPTR 34A0 DCH5DPTR DS60001156H-page 91 34B0 DCH5CSIZ 34C0 DCH5CPTR 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — —
Virtual Address (BF88_#) 34E0 DCH6CON 34F0 DCH6ECON 3510 DCH6INT DCH6SSA 3520 DCH6DSA 3530 DCH6SSIZ 3540 DCH6DSIZ 3550 DCH6SPTR 3560 DCH6DPTR 3570 DCH6CSIZ 3580 DCH6CPTR 3590 DCH6DAT 2009-2013 Microchip Technology Inc.
Virtual Address (BF88_#) 35F0 DCH7SSIZ 3600 DCH7DSIZ 3610 DCH7SPTR 3620 DCH7DPTR 3630 DCH7CSIZ 3640 DCH7CPTR 3650 DMA CHANNELS 0-7 REGISTER MAP (CONTINUED) DCH7DAT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000
Virtual Address (BF80_#) COMPARATOR REGISTER MAP A000 CM1CON A010 CM2CON A060 CMSTAT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 — 31:16 — — — — — — — — 15:0 ON COE CPOL — — — — COUT 31:16 — — — — — — — — 15:0 ON COE CPOL — — — — COUT 31:16 — — — — — — — 15:0 — — SIDL — — — — 20/4 19/3 18/2 17/1 16/0 — — — — — — — EVPOL<1:0> — CREF — — — CCH<1:0> — — All Resets Register Name(1) Bit Range Bits 0000 00C
Virtual Address (BF80_#) FLASH CONTROLLER REGISTER MAP F410 F440 NVMSRC ADDR 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — 31:16 — — — — — — — — — — — — 15:0 WR WREN WRERR LVDERR LVDSTAT — — — — — — — NVMOP<3:0> 31:16 0000 0000 0000 NVMADDR<31:0> 15:0 31:16 0000 0000 NVMDATA<31:0> 15:0 31:16 0000 0000 NVMSRCADDR<31:0> 15:0 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’.
Virtual Address (BF88_#) Register Name(1) 6000 TRISA 6010 PORTA 6020 LATA 6030 ODCA PORTA REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — —
Virtual Address (BF88_#) Register Name(1) 6080 TRISC 6090 PORTC 60A0 LATC 60B0 ODCC PORTC REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — —
Virtual Address (BF88_#) Register Name(1) 60C0 TRISD 60D0 PORTD 60E0 LATD 60F0 ODCD PORTD REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31/15 30/14 29/13 28/12 31:16 — — — — — — — — — — — — — — — — 0000
Virtual Address (BF88_#) Register Name(1) 6100 TRISE 6110 PORTE 6120 LATE 6130 ODCE PORTE REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — — — — — — — — — — 0000
Virtual Address (BF88_#) Register Name(1) 6140 TRISF PORTF REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 6150 PORTF 6160 LATF 6170 ODCF 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — 15:0 — — — — — — — — — — TRISF5 31:16 —
Virtual Address (BF88_#) Register Name(1) 6180 TRISG PORTG REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES 6190 PORTG 61A0 LATG 61B0 ODCG 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 31:16 — — — — — — — — 15:0 — — — — — — TRISG9 TRISG8
Virtual Address (BF88_#) CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES 61C0 CNCON 61D0 CNEN 61E0 CNPUE 31/15 30/14 31:16 — 15:0 ON 31:16 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — —
Virtual Address (BF80_#) Register Name(1) 7000 PMCON PARALLEL MASTER PORT REGISTER MAP 7010 PMMODE 7020 PMADDR 7030 PMDOUT 7040 PMDIN 7050 PMAEN 7060 PMSTAT 31/15 30/14 29/13 31:16 — — — 15:0 ON — SIDL 31:16 — — — 15:0 BUSY 31:16 — IRQM<1:0> — — 28/12 27/11 — — ADRMUX<1:0> — — INCM<1:0> — — 26/10 25/9 24/8 23/7 22/6 — — — — — PMPTTL PTWREN PTRDEN — — — MODE16 — — MODE<1:0> — — — — 20/4 19/3 18/2 17/1 16/0 — — — — — — ALP CS2P CS1P —
Virtual Address (BF88_#) 4010 CHEACC(1) CHETAG(1) 4030 CHEMSK(1) 4040 CHEW0 4050 CHEW1 4060 CHEW2 4070 CHEW3 4080 CHELRU 4090 CHEHIT 40A0 CHEMIS 40C0 CHEPFABT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 — — — — — — — — — 15:0 — — — — — — — 31:16 CHEWEN — — — — — — — 15:0 — — — — — — — — — — — — — — — 31:16 LTAGBOOT 15:0 31:16 DCSZ<1:0> — — — — — — — 31:16 31:16 31:16 31:16 15:0 — — — PREFEN<1:0> — — — —
Virtual Address (BF80_#) Register Name(1) 0200 RTCCON RTCTIME 0230 RTCDATE 0240 ALRMTIME 0250 ALRMDATE Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 31:16 — 15:0 ON 31:16 15:0 — — — — — — SIDL — — — — — — — ALRMEN CHIME PIV ALRMSYNC 31:16 25/9 24/8 — — — — — — SEC10<3:0> SEC01<3:0> YEAR10<3:0> YEAR01<3:0> 15:0 DAY10<3:0> DAY01<3:0> 31:16 HR10<3:0> HR01<3:0> 15:0 SEC10<3:0> — — DAY10<3:0> RTSECSEL RTCCLKON — — — 19/3 18/2 17/1 16/0 — —
2FF0 DEVCFG3 2FF4 DEVCFG2 2FF8 DEVCFG1 2FFC DEVCFG0 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 — — — FCANIO FETHIO FMIIEN — — — — — FSRSSEL<2:0> — — — — FPLLODIV<2:0> xxxx — FPLLIDIV<2:0> xxxx 31:16 FVBUSONIO FUSBIDIO 15:0 18/2 17/1 16/0 xxxx USERID<15:0> 31:16 — — — — — 15:0 UPLLEN — — — — 31:16 — — — — — — 15:0 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC 31:16 — — — — — — — — 15:0 — CP PWP<3:0> — — — — UPLLIDIV<2:
Virtual Address (BF88_#) Register Name(1) 5040 U1OTGIR(2) 5050 U1OTGIE 5070 U1OTGCON 5080 U1PWRC U1IR(2) 5200 5210 U1IE U1EIR(2) 5240 U1EIE U1STAT(3) 5250 5260 5270 DS60001156H-page 107 5280 U1CON U1ADDR U1BDTP1 U1FRML Legend: Note 1: 2: 3: 4: (3) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 22/6 21/5 — — 20/4 31:16 — — — — — — — — — 15:0 — — — — — — — — IDIF 31:16 — — — — — — — — — 15:0 — — — — — — — — IDIE 31:16 — — — — —
Virtual Address (BF88_#) Register Name(1) 5290 U1FRMH(3) U1TOK 52B0 52D0 52E0 U1SOF U1BDTP2 U1BDTP3 U1CNFG1 5300 U1EP0 5310 U1EP1 5320 U1EP2 5330 U1EP3 5340 U1EP4 5350 U1EP5 5360 U1EP6 2009-2013 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name(1) 53B0 U1EP11 53C0 U1EP12 53D0 U1EP13 USB REGISTER MAP (CONTINUED) 53E0 U1EP14 53F0 U1EP15 Legend: Note 1: 2: 3: 4: 20/4 19/3 18/2 17/1 16/0 All Resets Bits Bit Range 2009-2013 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name(1) B000 C1CON C1CFG B020 C1INT B030 B050 B060 C1VEC C1TREC C1FSTAT C1RXOVF B070 C1TMR B080 C1RXM0 B090 B0A0 2009-2013 Microchip Technology Inc.
Virtual Address (BF88_#) B100 C1FLTCON4 B110 C1FLTCON5 B120 C1FLTCON6 B130 C1FLTCON7 B140 B340 CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) C1RXFn (n = 0-31) C1FIFOBA 31/15 30/14 29/13 28/12 27/1
Virtual Address (BF88_#) Register Name(1) C000 C2CON C010 C2CFG C020 C030 C040 C050 C060 C070 C2INT C2VEC C2TREC C2FSTAT C2RXOVF C2TMR C2RXM0 C0A0 C2RXM1 2009-2013 Microchip Technology Inc.
Virtual Address (BF88_#) C100 C2FLTCON4 C110 C2FLTCON5 C120 C2FLTCON6 C130 C2FLTCON7 C140 C340 CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) C2RXFn (n = 0-31) C2FIFOBA C2FIFOINTn (n = 0-31) 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 MSEL19<1:0> FSEL19<4:0> FLTEN18 MSEL18<1:0> FSEL18<4:0> 0000 15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1
Virtual Address (BF88_#) Register Name(1) 9000 ETHCON1 9010 ETHCON2 9020 9030 9040 9050 9060 9070 9080 9090 90A0 ETHTXST ETHRXST ETHHT0 ETHHT1 ETHPMM0 ETHPMM1 ETHPMCS ETHPMO ETHRXFC 2009-2013 Microchip Technology Inc.
Virtual Address (BF88_#) Register Name(1) 90E0 ETHSTAT ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — —
Register Name(1) 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 4.2 Control Registers Register 4-1 through Register 4-8 are used for setting the RAM and Flash memory partitions for data and code.
PIC32MX5XX/6XX/7XX REGISTER 4-2: Bit Range 31:24 23:16 15:8 7:0 BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDKPBA<15:8> R-0 R-0 BMXDKPBA<7:0> Legend: R = Read
PIC32MX5XX/6XX/7XX REGISTER 4-3: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 BMXDUDBA<15:8> R-0 7:0 BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER R-0 R-0 R-0 R-0 BMXDUDBA<7:0> Legend: R = Readabl
PIC32MX5XX/6XX/7XX REGISTER 4-4: Bit Range 31:24 23:16 15:8 7:0 BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDUPBA<15:8> R-0 R-0 BMXDUPBA<7:0> Legend: R = Readab
PIC32MX5XX/6XX/7XX REGISTER 4-5: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXDRMSZ<31:24> R R R R R BMXDRMSZ<23:16> R R R R R BMXDRMSZ<15:8> R 7:0 BMXDRMSZ: DATA RAM SIZE REGISTER R R R R BMXDRMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is
PIC32MX5XX/6XX/7XX REGISTER 4-7: Bit Range 31:24 23:16 15:8 7:0 BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R R R R R R Bit Bit 28/20/12/4 27/19/11/3 R Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R R R R R R R R R R R R R BMXPFMSZ<31:24> R R BMXPFMSZ<23:16> R R R R R R R R BMXPFMSZ<15:8> R R BMXPFMSZ<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’
PIC32MX5XX/6XX/7XX 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Program Memory” (DS60001121) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX 5.
PIC32MX5XX/6XX/7XX REGISTER 5-2: Bit Range 31:24 23:16 15:8 7:0 NVMKEY: PROGRAMMING UNLOCK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 W-0 W-0 W-0 Bit Bit 28/20/12/4 27/19/11/3 W-0 W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<31:24> W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<23:16> W-0 NVMKEY<15:8> W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read
PIC32MX5XX/6XX/7XX REGISTER 5-4: Bit Range 31:24 23:16 15:8 7:0 NVMDATA: FLASH PROGRAM DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<23:16> R/W-0 NVMDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<7:0> Leg
PIC32MX5XX/6XX/7XX 6.0 RESETS Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Resets” (DS60001118) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.
PIC32MX5XX/6XX/7XX 6.
PIC32MX5XX/6XX/7XX REGISTER 6-2: Bit Range 31:24 23:16 15:8 7:0 RSWRST: SOFTWARE RESET REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC — — — — — — — SWRST(1) Legend: HC = Cleared b
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 130 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Interrupts” (DS60001108) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices.
PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION Interrupt Source(1) IRQ Number Vector Number Interrupt Bit Location Flag Enable Priority IEC0<0> IPC0<4:2> Sub-Priority Highest Natural Order Priority CT – Core Timer Interrupt 0 0 IFS0<0> IPC0<1:0> CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> INT0 – External Interrupt 0 3 3 IFS0<3> IEC0<3> IPC0<28:26>
PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Source(1) IRQ Number Vector Number Interrupt Bit Location Flag Enable Priority Sub-Priority AD1 – ADC1 Convert Done 33 27 IFS1<1> IEC1<1> IPC6<28:26> IPC6<25:24> PMP – Parallel Master Port 34 28 IFS1<2> IEC1<2> IPC7<4:2> IPC7<1:0> CMP1 – Comparator Interrupt 35 29 IFS1<3> IEC1<3> IPC7<12:10> IPC7<9:8> CMP2 – Comparator Interrupt 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16> U3E – U
PIC32MX5XX/6XX/7XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) Interrupt Source(1) IRQ Number Vector Number Interrupt Bit Location Flag Enable Priority Sub-Priority IC3E – Input Capture 3 Error 63 13 IFS1<31> IEC1<31> IPC3<12:10> IPC3<9:8> IC4E – Input Capture 4 Error 64 17 IFS2<0> IEC2<0> IPC4<12:10> IPC4<9:8> IC4E – Input Capture 5 Error 65 21 IFS2<1> IEC2<1> IPC5<12:10> IPC5<9:8> PMPE – Parallel Master Port Error 66 28 IFS2<2> IEC2<2> IPC7<4:2> IPC7<1
PIC32MX5XX/6XX/7XX 7.
PIC32MX5XX/6XX/7XX REGISTER 7-2: Bit Range 31:24 23:16 15:8 7:0 INTSTAT: INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 — — Legend: R = Readable bit -n = Value at POR RIPL<2:0>(1) R/W-
PIC32MX5XX/6XX/7XX REGISTER 7-4: Bit Range 31:24 23:16 15:8 7:0 IFSx: INTERRUPT FLAG STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 R/W-0 IFS31 IFS30 IFS29 R/W-0 R/W-0 R/W-0 IFS23 IFS22 IFS21 Note: 31:24 23:16 15:8 7:0 Note: Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 IFS28 IFS27 IFS26 IFS25 IFS24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS20 IFS19 IFS18 IFS17 IFS16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS14 IFS13 IFS12 IFS11 IFS10 IF
PIC32MX5XX/6XX/7XX REGISTER 7-6: Bit Range IPCx: INTERRUPT PRIORITY CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 — — — U-0 U-0 U-0 31:24 23:16 15:8 7:0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 W = Writable bit ‘1’ = Bit is set R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 IP03<2:0> R/W-0 R/W-0 IS03<1:0> R/W-0 R/W-0 R/W-0 R/W-0 IP02<2
PIC32MX5XX/6XX/7XX REGISTER 7-6: IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED) bit 12-10 IP01<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 • • • bit 9-8 bit 7-5 bit 4-2 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS01<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as ‘0’ IP00<2:0>: Interrupt Priority bits
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 140 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 8.
PIC32MX5XX/6XX/7XX 8.
PIC32MX5XX/6XX/7XX REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = Internal Fast
PIC32MX5XX/6XX/7XX REGISTER 8-1: bit 2 bit 1 bit 0 Note: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) UFRCEN: USB FRC Clock Enable bit 1 = Enable FRC as the clock source for the USB clock source 0 = Use the Primary Oscillator or USB PLL as the USB clock source SOSCEN: Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switc
PIC32MX5XX/6XX/7XX REGISTER 8-2: Bit Range 31:24 23:16 15:8 7:0 OSCTUN: FRC TUNING REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — R/W-0 (1) TUN<5:0> Legend: R = Readable bit W
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 146 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 9.0 PREFETCH CACHE Prefetch cache increases performance for applications executing out of the cacheable program Flash memory regions by implementing instruction caching, constant data caching and instruction prefetching. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4.
PIC32MX5XX/6XX/7XX 9.
PIC32MX5XX/6XX/7XX REGISTER 9-2: Bit Range 31:24 23:16 15:8 7:0 CHEACC: CACHE ACCESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 CHEWEN — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CHEIDX<3:0> Legend: R = Readab
PIC32MX5XX/6XX/7XX REGISTER 9-3: Bit Range 31:24 23:16 15:8 7:0 CHETAG: CACHE TAG REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 LTAGBOOT — — — — — — — R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x LTAG<19:12> R/W-x R/W-x R/W-x R/W-x R/W-x LTAG<11:4> R/W-x R/W-x R/W-x R/W-x LTAG<3:0> R/W-0 R/W-0 R/W-1 U-0 LVALID LLOCK LTYPE
PIC32MX5XX/6XX/7XX REGISTER 9-4: Bit Range 31:24 23:16 15:8 7:0 CHEMSK: CACHE TAG MASK REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LMASK<10:3> R/W-0 R/W-0 R/W-0 LMASK<2:0> U-0 U-0 U-0 U-0 U-0 — — — — — Legend: R = Readabl
PIC32MX5XX/6XX/7XX REGISTER 9-6: Bit Range 31:24 23:16 15:8 7:0 CHEW1: CACHE WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-x R/W-x R/W-x Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1<31:24> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1<23:16> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1<15:8> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW1<7:0> Legend: R = Readable bit
PIC32MX5XX/6XX/7XX REGISTER 9-8: Bit Range 31:24 23:16 15:8 7:0 CHEW3: CACHE WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-x R/W-x R/W-x Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3<31:24> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3<23:16> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3<15:8> R/W-x R/W-x R/W-x R/W-x R/W-x CHEW3<7:0> Legend: R = Readable bit
PIC32MX5XX/6XX/7XX REGISTER 9-10: Bit Range 31:24 23:16 15:8 7:0 CHEHIT: CACHE HIT STATISTICS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-x R/W-x R/W-x Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT<31:24> R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT<23:16> R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT<15:8> R/W-x R/W-x R/W-x R/W-x R/W-x CHEHIT<7:0> Leg
PIC32MX5XX/6XX/7XX REGISTER 9-12: Bit Range 31:24 23:16 15:8 7:0 CHEPFABT: PREFETCH CACHE ABORT STATISTICS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-x R/W-x R/W-x Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CHEPFABT<31:24> R/W-x R/W-x R/W-x R/W-x R/W-x CHEPFABT<23:16> R/W-x R/W-x R/W-x R/W-x R/W-x CHEPFABT<15:8> R/W-x R/W-x R/W-x R/W-x R/W-
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 156 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 10.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. “Direct Memory Access (DMA) Controller” (DS60001117) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX 10.
PIC32MX5XX/6XX/7XX REGISTER 10-2: Bit Range 31:24 23:16 15:8 7:0 DMASTAT: DMA STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — RDWR DMACH<2:0> Legend: R = Readable bit W
PIC32MX5XX/6XX/7XX REGISTER 10-4: Bit Range 31:24 23:16 15:8 7:0 DCRCCON: DMA CRC CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 R/W-0 R/W-0 BYTO<1:0> Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 R/W-0 R/W-0 (1) — — WBO — — BITO U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 R/W-0 U-0 U-0 PLEN<4:0> CRCEN CRCAPP(1) CR
PIC32MX5XX/6XX/7XX REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) bit 6 CRCAPP: CRC Append Mode bit(1) 1 = The DMA transfers data from the source into the CRC but not to the destination.
PIC32MX5XX/6XX/7XX REGISTER 10-5: Bit Range 31:24 23:16 15:8 7:0 DCRCDATA: DMA CRC DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<31:24> R/W-0 R/W-0 DCRCDATA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA<7:0> L
PIC32MX5XX/6XX/7XX REGISTER 10-7: Bit Range 31:24 23:16 15:8 7:0 DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 CHBUSY — — — — — — CHCHNS(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 CHEN(2) CHAED
PIC32MX5XX/6XX/7XX REGISTER 10-8: Bit Range 31:24 23:16 DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHAIRQ<7:0> 15:8 R/W-1 CHSIRQ<7:0>(1) 7:0 S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CFORCE CABOR
PIC32MX5XX/6XX/7XX REGISTER 10-9: Bit Range 31:24 23:16 15:8 7:0 DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 10-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER (CONTINUED) bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit 1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ) 0 = No interrupt is pending bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2) 0 = No interrupt is pending bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag
PIC32MX5XX/6XX/7XX REGISTER 10-10: DCHxSSA: DMA CHANNEL ‘x’ SOURCE START ADDRESS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<31:24> 23:16 R/W-0 R/W-0 CHSSA<23:16> 15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA<15:8> 7:0 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 10-12: DCHxSSIZ: DMA CHANNEL ‘x’ SOURCE SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSIZ<15:8> 7:0 R/W-0 CHSSIZ<7:0> Lege
PIC32MX5XX/6XX/7XX REGISTER 10-14: DCHxSPTR: DMA CHANNEL ‘x’ SOURCE POINTER REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHSPTR<15:8> 7:0 R-0 R-0 CHSPTR<7:0> Legend: R = Readable bit -n = Val
PIC32MX5XX/6XX/7XX REGISTER 10-16: DCHxCSIZ: DMA CHANNEL ‘x’ CELL-SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHCSIZ<15:8> 7:0 R/W-0 CHCSIZ<7:0> Legend
PIC32MX5XX/6XX/7XX REGISTER 10-18: DCHxDAT: DMA CHANNEL ‘x’ PATTERN DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHPDAT<7:0> Legend: R =
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 172 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 11.0 USB ON-THE-GO (OTG) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. “USB OnThe-Go (OTG)” (DS60001126) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX FIGURE 11-1: PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM USBEN FRC Oscillator 8 MHz Typical USB Suspend CPU Clock Not POSC Sleep TUN<5:0>(4) Primary Oscillator (POSC) UFIN(5) Div x PLL Div 2 UFRCEN(3) OSC1 UPLLEN(6) UPLLIDIV(6) USB Suspend OSC2 To Clock Generator for Core and Peripherals Sleep or Idle (PB Out)(1) USB Module SRP Charge Bus USB Voltage Comparators SRP Discharge 48 MHz USB Clock(7) Full-Speed Pull-up D+(2) Registers and Control Interface Host Pull-do
PIC32MX5XX/6XX/7XX 11.
PIC32MX5XX/6XX/7XX REGISTER 11-2: Bit Range 31:24 23:16 15:8 7:0 U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTV
PIC32MX5XX/6XX/7XX REGISTER 11-3: Bit Range 31:24 23:16 15:8 7:0 U1OTGSTAT: USB OTG STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0 ID — LSTATE — SESVD SESEND — VBUSVD Legend:
PIC32MX5XX/6XX/7XX REGISTER 11-4: Bit Range 31:24 23:16 15:8 7:0 U1OTGCON: USB OTG CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 DPPULUP DMPULUP DPPULDWN DMPULDWN R/W-0 R/W-0 R/W-0 R/W-0 V
PIC32MX5XX/6XX/7XX REGISTER 11-5: Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U1PWRC: USB POWER CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UACTPND — — USLPGRD USBBUSY — USUSPEND U
PIC32MX5XX/6XX/7XX REGISTER 11-6: Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U1IR: USB INTERRUPT REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R-0 IDLEIF TRNIF(3) SOFIF
PIC32MX5XX/6XX/7XX REGISTER 11-7: Bit Range 31:24 23:16 15:8 7:0 U1IE: USB INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE
PIC32MX5XX/6XX/7XX REGISTER 11-8: Bit Range 31:24 23:16 15:8 7:0 U1EIR: USB ERROR INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS
PIC32MX5XX/6XX/7XX REGISTER 11-9: Bit Range 31:24 23:16 15:8 7:0 U1EIE: USB ERROR INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BTSEE BMXEE DMAEE BTOEE
PIC32MX5XX/6XX/7XX REGISTER 11-10: U1STAT: USB STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-x R-x R-x R-x R-x R-x U-0 U-0 DIR PPBI — — ENDPT<3:0> Legend: R = Readable bit W =
PIC32MX5XX/6XX/7XX REGISTER 11-11: U1CON: USB CONTROL REGISTER Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE PKTDIS(4) SE0 TOKBUSY(1,5) USBRST HOSTEN(2)
PIC32MX5XX/6XX/7XX REGISTER 11-11: U1CON: USB CONTROL REGISTER (CONTINUED) bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Even/Odd buffer pointers to the Even buffer descriptor banks 0 = Even/Odd buffer pointers are not reset bit 0 USBEN: USB Module Enable bit(4) 1 = USB module and supporting circuitry enabled 0 = USB module and supporting circuitry disabled SOFEN: SOF Enable bit(5) 1 = SOF token sent every 1 ms 0 = SOF token disabled Note 1: 2: 3: 4: 5: Software is required to check this bit
PIC32MX5XX/6XX/7XX REGISTER 11-12: U1ADDR: USB ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPDEN DEVADDR<6:0> Legend: R = Readable
PIC32MX5XX/6XX/7XX REGISTER 11-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — FRMH<2:0> Legend: R = Readable b
PIC32MX5XX/6XX/7XX REGISTER 11-16: U1SOF: USB SOF THRESHOLD REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT<7:0> Legend: R = Readable bit W
PIC32MX5XX/6XX/7XX REGISTER 11-18: U1BDTP2: USB BUFFER DESCRIPTOR TABLE PAGE 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDTPTRH<23:16> Le
PIC32MX5XX/6XX/7XX REGISTER 11-20: U1CNFG1: USB CONFIGURATION 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 UTEYE UOEMON — USBSIDL — — — UASUS
PIC32MX5XX/6XX/7XX REGISTER 11-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPD RETRYDIS — EPCONDIS
PIC32MX5XX/6XX/7XX 12.0 I/O PORTS General purpose I/O pins are the simplest of peripherals. They allow the PIC32 MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin.
PIC32MX5XX/6XX/7XX 12.1 Parallel I/O (PIO) Ports All port pins have three registers (TRIS, LAT and PORT) that are directly associated with their operation. TRIS is a Data Direction or Tri-State Control register that determines whether a digital pin is an input or an output. Setting a TRISx register bit = 1, configures the corresponding I/O pin as an input; setting a TRISx register bit = 0, configures the corresponding I/O pin as an output. All port I/O pins are defined as inputs after a device Reset.
PIC32MX5XX/6XX/7XX 12.
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 196 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 13.0 TIMER1 This family of PIC32 devices features one synchronous/ asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the low-power Secondary Oscillator (SOSC) for Real-Time Clock (RTC) applications. The following modes are supported: Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices.
PIC32MX5XX/6XX/7XX 13.
PIC32MX5XX/6XX/7XX REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED) bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 Unimplemented: Read as ‘0’ bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0: This bit is ignored.
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 200 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 14.0 TIMER2/3, TIMER4/5 Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14.
PIC32MX5XX/6XX/7XX FIGURE 14-2: TIMER2/3 AND TIMER4/5 BLOCK DIAGRAM (32-BIT) Reset TMRy MS Half Word ADC Event Trigger(3) Equal Sync LS Half Word 32-bit Comparator PRy TyIF Event Flag TMRx PRx 0 1 Q D TGATE (TxCON<7>) Q TCS (TxCON<1>) TGATE (TxCON<7>) ON (TxCON<15>) TxCK(2) x1 Gate Sync PBCLK 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS (TxCON<6:4>) Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use of ‘y’
PIC32MX5XX/6XX/7XX 14.
PIC32MX5XX/6XX/7XX REGISTER 14-1: TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED) T32: 32-Bit Timer Mode Select bit(2) 1 = Odd numbered and even numbered timers form a 32-bit timer 0 = Odd numbered and even numbered timers form a separate 16-bit timer bit 3 bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer Clock Source Select bit(3) 1 = External clock from TxCK pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as ‘0’ Note 1: When using the 1:1 PBCLK divisor, the user’s software should
PIC32MX5XX/6XX/7XX 15.0 INPUT CAPTURE • Capture timer value on every edge (rising and falling) • Capture timer value on every edge (rising and falling), specified edge first. • Prescaler capture event modes: - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source.
PIC32MX5XX/6XX/7XX 15.
PIC32MX5XX/6XX/7XX REGISTER 15-1: bit 2-0 Note 1: ICXCON: INPUT CAPTURE ‘X’ CONTROL REGISTER (CONTINUED) ICM<2:0>: Input Capture Mode Select bits 111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode) 110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter 101 = Prescaled Capture Event mode – every sixteenth rising edge 100 = Prescaled Capture Event mode – every fourth rising edge 011 = Simple Capture Event mode – every rising edge 010 = Simple Ca
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 208 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 16.0 OUTPUT COMPARE The Output Compare module is used to generate a single pulse or a series of pulses in response to selected time base events. For all modes of operation, the Output Compare module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the Output Compare module generates an event based on the selected mode of operation.
PIC32MX5XX/6XX/7XX 16.
PIC32MX5XX/6XX/7XX 17.0 SERIAL PERIPHERAL INTERFACE (SPI) The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, Shift registers, display drivers, Analog-to-Digital Converters, etc. The PIC32 SPI module is compatible with Motorola® SPI and SIOP interfaces. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices.
PIC32MX5XX/6XX/7XX 17.
PIC32MX5XX/6XX/7XX REGISTER 17-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED) ENHBUF: Enhanced Buffer Enable bit(2) 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled bit 15 ON: SPI Peripheral On bit(1) 1 = SPI Peripheral is enabled 0 = SPI Peripheral is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters in Idle mode 0 = Continue operation in Idle mode bit 12 DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by th
PIC32MX5XX/6XX/7XX REGISTER 17-2: Bit Range 31:24 23:16 15:8 7:0 SPIxSTAT: SPI STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 U-0 R-0 SPITUR — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 RXBUFELM<4:0> R-0 TXBUFELM<4:0> U-0 R-0 U-0 — — — — SPIBUSY — — R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0 SRMT SPIROV SPIRBE — SPITBE — SPITBF SP
PIC32MX5XX/6XX/7XX REGISTER 17-2: bit 1 SPIxSTAT: SPI STATUS REGISTER SPITBF: SPI Transmit Buffer Full Status bit 1 = Transmit not yet started, SPITXB is full 0 = Transmit buffer is not full Standard Buffer Mode: Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB. Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 216 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 18.0 INTER-INTEGRATED CIRCUIT™ (I2C™) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “InterIntegrated Circuit™ (I2C™)” (DS60001116) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX FIGURE 18-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop bit Detect Write Start and Stop bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read PBCLK DS60001156H-page 218 2009-2013 Microchip Techn
PIC32MX5XX/6XX/7XX 18.
PIC32MX5XX/6XX/7XX REGISTER 18-1: I2CXCON: I2C™ CONTROL REGISTER (CONTINUED) bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit.
PIC32MX5XX/6XX/7XX REGISTER 18-2: Bit Range 31:24 23:16 15:8 7:0 I2CXSTAT: I2C™ STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-
PIC32MX5XX/6XX/7XX REGISTER 18-2: I2CXSTAT: I2C™ STATUS REGISTER (CONTINUED) bit 5 D_A: Data/Address bit (when operating as I2C slave) This bit is cleared by hardware upon a device address match, and is set by hardware by reception of the slave byte. 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address bit 4 P: Stop bit This bit is set or cleared by hardware when a Start, Repeated Start, or Stop condition is detected.
PIC32MX5XX/6XX/7XX 19.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX Figure 19-2 and Figure 19-3 illustrate typical receive and transmit timing for the UART module.
PIC32MX5XX/6XX/7XX 19.
PIC32MX5XX/6XX/7XX REGISTER 19-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55); cleared by hardware upon completion 0 = Baud rate measurement disabled or completed bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode – 4x baud clock enabled 0 = Standard Speed mode – 16x b
PIC32MX5XX/6XX/7XX REGISTER 19-2: Bit Range 31:24 23:16 15:8 7:0 UxSTA: UARTx STATUS AND CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ADM_EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1 TRMT ADDR<7:0> R/W-0 R/W-0 UTXISEL<1:0> R/W-0 R/W-0 URXISEL<1:0> R/W-0 R/W-0 R/W-0, HC R/W-0 UTXINV URXEN UTXBRK UTXEN UTXBF R
PIC32MX5XX/6XX/7XX REGISTER 19-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 8 TRMT: Transmit Shift Register is Empty bit (read-only) 1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit 11 = Reserved 10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full
PIC32MX5XX/6XX/7XX 20.0 PARALLEL MASTER PORT (PMP) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Parallel Master Port (PMP)” (DS60001128) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX 20.
PIC32MX5XX/6XX/7XX REGISTER 20-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 5 ALP: Address Latch Polarity bit(2) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 Unimplemented: Read as ‘0’ bit 3 CS1P: Chip Select 0 Polarity bit(2) 1 = Active-high (PMCS1) 0 = Active-low (PMCS1) bit 2 Unimplemented: Read as ‘0’ bit 1 WRSP: Write Strobe Polarity bit For Slave Modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe act
PIC32MX5XX/6XX/7XX REGISTER 20-2: Bit Range 31:24 23:16 15:8 PMMODE: PARALLEL PORT MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 BUSY R/W-0 7:0 IRQM<1:0> R/W-0 (1) R/W-0 WAITB<1:0> INCM<1:0> R/W-0 R/W-0 (1) — MODE<1:0> R/W-0 R
PIC32MX5XX/6XX/7XX REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED) bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1) 1111 = Wait of 16 TPB • • • 0001 = Wait of 2 TPB 0000 = Wait of 1 TPB (default) bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1) 11 = Wait of 4 TPB 10 = Wait of 3 TPB 01 = Wait of 2 TPB 00 = Wait of 1 TPB (default) For Read operations: 11 = Wait of 3 TPB 10 = Wait of 2 TPB 01 = Wait of 1 TPB 00 = Wait of 0 TPB (default) Note 1: Whenev
PIC32MX5XX/6XX/7XX REGISTER 20-3: Bit Range 31:24 23:16 15:8 7:0 PMADDR: PARALLEL PORT ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — CS1 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<10:8> R/W-0 R/W-0 R/W-0 ADDR<7:0> Legend: R
PIC32MX5XX/6XX/7XX REGISTER 20-4: Bit Range 31:24 23:16 15:8 7:0 PMAEN: PARALLEL PORT PIN ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — PTEN14 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<10:8> R/W-0 R/W-0 R/W-0 PTEN<7:0> Lege
PIC32MX5XX/6XX/7XX REGISTER 20-5: Bit Range 31:24 23:16 15:8 7:0 PMSTAT: PARALLEL PORT STATUS REGISTER (ONLY SLAVE MODES) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R/W-0, HSC U-0 U-0 R-0 R-0 R-0 R-0 IB0F IBF IBOV — — IB3F IB2F IB1F R-1 R/W-0, HSC U-0 U-0 R-1 R-1 R-1 R-1
PIC32MX5XX/6XX/7XX 21.0 REAL-TIME CLOCK AND CALENDAR (RTCC) Key features of the RTCC module include: • • • • • Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX 21.
PIC32MX5XX/6XX/7XX REGISTER 21-1: RTCCON: RTC CONTROL REGISTER (CONTINUED) RTCWREN: RTC Value Registers Write Enable bit(4) 1 = RTC Value registers can be written to by the user 0 = RTC Value registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read.
PIC32MX5XX/6XX/7XX REGISTER 21-2: Bit Range 31:24 23:16 15:8 RTCALRM: RTC ALARM CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R-0 R/W-0 R/W-0 CHIME(2) R/W-0 (2) R/W-0 ALRMEN(1,2) R/W-0 (2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 7:0 PIV ALRMSYNC(3) R/W-0 AMA
PIC32MX5XX/6XX/7XX REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED) ARPT<7:0>: Alarm Repeat Counter Value bits(2) 11111111 = Alarm will trigger 256 times bit 7-0 • • • 00000000 = Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1. Note 1: 2: 3: Note: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and CHIME = 0.
PIC32MX5XX/6XX/7XX REGISTER 21-3: Bit Range 31:24 23:16 15:8 7:0 RTCTIME: RTC TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> HR01<3:0> R/W-x MIN10<3:0> R/W-x R/W-x U-0 U-0 — — R/W-x R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — SEC10<3:0> R/W-x R/W-x
PIC32MX5XX/6XX/7XX REGISTER 21-4: Bit Range 31:24 23:16 15:8 7:0 RTCDATE: RTC DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YEAR10<3:0> R/W-x YEAR01<3:0> MONTH10<3:0> R/W-x R/W-x U-0 U-0 — — R/W-x R/W-x R/W-x MONTH01<3:0> R/W-x R/W-x R/W-x U-0 U-0 R/W-x R/W-x — — DAY10<3:0> R/W-x R/W-x DAY01<3:0
PIC32MX5XX/6XX/7XX REGISTER 21-5: Bit Range 31:24 23:16 15:8 7:0 ALRMTIME: ALARM TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10<3:0> HR01<3:0> R/W-x MIN10<3:0> R/W-x R/W-x U-0 U-0 — — R/W-x R/W-x R/W-x MIN01<3:0> R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — SEC10<3:0> R/W-x R/
PIC32MX5XX/6XX/7XX REGISTER 21-6: Bit Range 31:24 23:16 15:8 7:0 ALRMDATE: ALARM DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 U-0 U-0 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 — — — — — — — — R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 R/W-x R/W-x — — — — MONTH10<3:0> R/W-x MONTH01<3:0> DAY10<1:0> R/W-x R/W-x DAY01<3:0> R/W-x R/W-x
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 246 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 22.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX FIGURE 22-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC FRC 2 1 TAD ADCS<7:0> 0 8 TPB ADC Conversion Clock Multiplier 2, 4,..., 512 DS60001156H-page 248 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 22.
PIC32MX5XX/6XX/7XX REGISTER 22-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED) bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto convert) 110 = Reserved 101 = Reserved 100 = Reserved 011 = CTMU ends sampling and starts conversion 010 = Timer 3 period match ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing the SAMP bit ends sampling and starts conversion bit 4 C
PIC32MX5XX/6XX/7XX REGISTER 22-2: Bit Range 31:24 23:16 15:8 AD1CON2: ADC CONTROL REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 OFFCAL — CSCNA — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFM ALTS VCFG<2:0> 7:0 Bit Bit 28/20/12/4 27/19/11/3 R-0 U-0 BUFS — R/W-0 S
PIC32MX5XX/6XX/7XX REGISTER 22-3: Bit Range 31:24 23:16 15:8 7:0 AD1CON3: ADC CONTROL REGISTER 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 U-0 — — — — R/W-0 U-0 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — — R/W-0 R/W-0 R/W-0 R/W R/W-0 SAMC<4:0>(1) R/W-0 R/W-0 R/W-0 ADCS<7:0>(2) Legend: R = Rea
PIC32MX5XX/6XX/7XX REGISTER 22-4: Bit Range 31:24 23:16 15:8 7:0 AD1CHS: ADC INPUT SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 U-0 U-0 U-0 CH0NB — — — R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 CH0SB<3:0> R/W-0 U-0 U-0 U-0 CH0NA — — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — CH0SA<3:0> Le
PIC32MX5XX/6XX/7XX REGISTER 22-5: Bit Range 31:24 23:16 15:8 7:0 AD1CSSL: ADC INPUT SCAN SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MX5XX/6XX/7XX 23.0 CONTROLLER AREA NETWORK (CAN) Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 34. “Controller Area Network (CAN)” (DS60001154) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX REGISTER 23-1: Bit Range 31:24 23:16 15:8 7:0 CiCON: CAN MODULE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 U-0 U-0 U-0 U-0 S/HC-0 R/W-1 — — — — ABAT R-0 R-0 R-1 OPMOD<2:0> R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 REQOP<2:0> R/W-0 U-0 U-0 U-0 CANCAP — — — U-0 — U-0 R-0 U-0 U-0 U-0 U-0 R/W-0 ON(1) — SIDLE — CANBUSY — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 23-1: CiCON: CAN MODULE CONTROL REGISTER (CONTINUED) bit 13 SIDLE: CAN Stop in Idle bit 1 = CAN Stops operation when system enters Idle mode 0 = CAN continues operation when system enters Idle mode bit 12 Unimplemented: Read as ‘0’ bit 11 CANBUSY: CAN Module is Busy bit 1 = The CAN module is active 0 = The CAN module is completely disabled bit 10-5 Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: Device Net Filter Bit Number bits 10011-11111 = Invalid Selection (compare
PIC32MX5XX/6XX/7XX REGISTER 23-2: Bit Range 31:24 23:16 15:8 7:0 CiCFG: CAN BAUD RATE CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — WAKFIL — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) SEG2PHTS R/W-0 SAM (2) R/W-0 SEG1PH<2:0> R/W-0 R/W-0 SJW<1:0>(3) Legend: SE
PIC32MX5XX/6XX/7XX REGISTER 23-2: CiCFG: CAN BAUD RATE CONFIGURATION REGISTER (CONTINUED) bit 10-8 PRSEG<2:0>: Propagation Time Segment bits(4) 111 = Length is 8 x TQ • • • 000 = Length is 1 x TQ bit 7-6 SJW<1:0>: Synchronization Jump Width bits(3) 11 = Length is 4 x TQ 10 = Length is 3 x TQ 01 = Length is 2 x TQ 00 = Length is 1 x TQ bit 5-0 BRP<5:0>: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/FSYS 111110 = TQ = (2 x 63)/FSYS • • • 000001 = TQ = (2 x 2)/FSYS 000000 = TQ = (2 x 1)/FSYS Note 1:
PIC32MX5XX/6XX/7XX REGISTER 23-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 CiINT: CAN INTERRUPT REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 IVRIE WAKIE CERRIE SERRIE RBOVIE — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — MODIE CTMRIE RBIE TBIE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 SERRIF (1) IVRIF WAKIF CERRIF RBOVIF — — — U-0
PIC32MX5XX/6XX/7XX REGISTER 23-3: CiINT: CAN INTERRUPT REGISTER (CONTINUED) bit 14 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit 1 = A bus wake-up activity interrupt has occurred 0 = A bus wake-up activity interrupt has not occurred bit 13 CERRIF: CAN Bus Error Interrupt Flag bit 1 = A CAN bus error has occurred 0 = A CAN bus error has not occurred bit 12 SERRIF: System Error Interrupt Flag bit 1 = A system error occurred (typically an illegal address was presented to the system bus) 0 = A syste
PIC32MX5XX/6XX/7XX REGISTER 23-4: Bit Range CiVEC: CAN INTERRUPT CODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 31:24 23:16 15:8 7:0 — — — U-0 R-1 R-0 FILHIT<4:0> R-0 ICODE<6:0>(1) — Legend: R = Readable bit W = Writab
PIC32MX5XX/6XX/7XX REGISTER 23-5: Bit Range 31:24 23:16 15:8 7:0 CiTREC: CAN TRANSMIT/RECEIVE ERROR COUNT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — TXBO TXBP RXBP TXWARN RXWARN EWARN R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TERRCNT<7:0> R-0 RERRCNT<7:0> Legend: R =
PIC32MX5XX/6XX/7XX REGISTER 23-7: Bit Range CiRXOVF: CAN RECEIVE FIFO OVERFLOW STATUS REGISTER Bit 31/23/15/7 31:24 23:16 15:8 7:0 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R-0 R-0 R-0 R-0 R-0 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 Bit 26/18/10/2 Bit 25/17/9/1 R-0 R-0 RXOVF26 RXOVF25 R-0 Bit 24/16/8/0 R-0 RXOVF24 R-0 R-0 R-0 R-0 R-0 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RX
PIC32MX5XX/6XX/7XX REGISTER 23-9: Bit Range 31:24 23:16 15:8 7:0 CiRXMn: CAN ACCEPTANCE FILTER MASK ‘n’ REGISTER (n = 0, 1, 2 OR 3) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SID<10:3> R/W-0 R/W-0 R/W-0 SID<2:0> U-0 R/W-0 U-0 — MIDE — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EID<17:
PIC32MX5XX/6XX/7XX REGISTER 23-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN3 R/W-0 23:16 FLTEN2 R/W-0 15:8 FLTEN1 R/W-0 7:0 FLTEN0 MSEL3<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL2<4:0> R/W-0 R/W-0 R/W-0 R/W-0 MSEL1<1:0> R/W-0 Bit 25/17/9/1 FSEL3<4:0> MSEL2<1:0> R/W-
PIC32MX5XX/6XX/7XX REGISTER 23-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 (CONTINUED) bit 15 FLTEN1: Filter 1 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL1<1:0>: Filter 1 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL1<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 •
PIC32MX5XX/6XX/7XX REGISTER 23-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN7 R/W-0 23:16 FLTEN6 R/W-0 15:8 FLTEN5 R/W-0 7:0 FLTEN4 MSEL7<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL6<4:0> R/W-0 R/W-0 R/W-0 R/W-0 MSEL5<1:0> R/W-0 Bit 25/17/9/1 FSEL7<4:0> MSEL6<1:0> R/W-
PIC32MX5XX/6XX/7XX REGISTER 23-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 (CONTINUED) bit 15 FLTEN5: Filter 17 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL5<1:0>: Filter 5 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL5<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 • •
PIC32MX5XX/6XX/7XX REGISTER 23-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN11 R/W-0 23:16 FLTEN10 R/W-0 15:8 FLTEN9 R/W-0 7:0 FLTEN8 MSEL11<1:0> R/W-0 FSEL11<4:0> R/W-0 R/W-0 R/W-0 MSEL10<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL9<1:0> R/W-0
PIC32MX5XX/6XX/7XX REGISTER 23-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2 (CONTINUED) bit 15 FLTEN9: Filter 9 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL9<1:0>: Filter 9 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL9<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30 •
PIC32MX5XX/6XX/7XX REGISTER 23-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN15 R/W-0 23:16 FLTEN14 R/W-0 15:8 FLTEN13 R/W-0 7:0 FLTEN12 MSEL15<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL14<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL13<1:0> R/W-0 Bit 25/17/9/1 FSEL15<4:0> MSEL14<1:0>
PIC32MX5XX/6XX/7XX REGISTER 23-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3 (CONTINUED) bit 15 FLTEN13: Filter 13 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL13<1:0>: Filter 13 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL13<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer
PIC32MX5XX/6XX/7XX ,4 REGISTER 23-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4 Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 FLTEN19 R/W-0 23:16 FLTEN18 R/W-0 15:8 FLTEN17 R/W-0 7:0 FLTEN16 MSEL19<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL18<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL17<1:0> R/W-0 Bit 25/17/9/1 FSEL19<4:0> MSEL18<
PIC32MX5XX/6XX/7XX REGISTER 23-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4 (CONTINUED) bit 15 FLTEN17: Filter 13 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL17<1:0>: Filter 17 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL17<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer
PIC32MX5XX/6XX/7XX REGISTER 23-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN23 R/W-0 23:16 FLTEN22 R/W-0 15:8 FLTEN21 R/W-0 7:0 FLTEN20 MSEL23<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL22<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL21<1:0> R/W-0 Bit 25/17/9/1 FSEL23<4:0> MSEL22<1:0>
PIC32MX5XX/6XX/7XX REGISTER 23-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5 (CONTINUED) bit 15 FLTEN21: Filter 21 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL21<1:0>: Filter 21 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL21<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer
PIC32MX5XX/6XX/7XX REGISTER 23-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN27 R/W-0 23:16 FLTEN26 R/W-0 15:8 FLTEN25 R/W-0 7:0 FLTEN24 MSEL27<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL26<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL25<1:0> R/W-0 Bit 25/17/9/1 FSEL27<4:0> MSEL26<1:0>
PIC32MX5XX/6XX/7XX REGISTER 23-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6 (CONTINUED) bit 15 FLTEN25: Filter 25 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL25<1:0>: Filter 25 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL25<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30
PIC32MX5XX/6XX/7XX REGISTER 23-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7 Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTEN31 R/W-0 23:16 FLTEN30 R/W-0 15:8 FLTEN29 R/W-0 7:0 FLTEN28 MSEL31<1:0> R/W-0 R/W-0 R/W-0 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FSEL30<4:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSEL29<1:0> R/W-0 Bit 25/17/9/1 FSEL31<4:0> MSEL30<1:0>
PIC32MX5XX/6XX/7XX REGISTER 23-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7 (CONTINUED) bit 15 FLTEN29: Filter 29 Enable bit 1 = Filter is enabled 0 = Filter is disabled bit 14-13 MSEL29<1:0>: Filter 29 Mask Select bits 11 = Acceptance Mask 3 selected 10 = Acceptance Mask 2 selected 01 = Acceptance Mask 1 selected 00 = Acceptance Mask 0 selected bit 12-8 FSEL29<4:0>: FIFO Selection bits 11111 = Message matching filter is stored in FIFO buffer 31 11110 = Message matching filter is stored in FIFO buffer 30
PIC32MX5XX/6XX/7XX REGISTER 23-18: CiRXFn: CAN ACCEPTANCE FILTER ‘n’ REGISTER 7 (n = 0 THROUGH 31) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID<10:3> R/W-x R/W-x R/W-x SID<2:0> U-0 R/W-0 U-0 — EXID — R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID<17:16>
PIC32MX5XX/6XX/7XX REGISTER 23-19: CiFIFOBA: CAN MESSAGE BUFFER BASE ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0(1) R-0(1) CiFIFOBA<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CiFIFOBA<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CiFIFOBA<15:8> R/
PIC32MX5XX/6XX/7XX REGISTER 23-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (n = 0 THROUGH 31) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — U-0 S/HC-0 S/HC-0 U-0 U-0 FSIZE<4:0>(1) R/W-0 DONLY U-0 (1) U-0 — FRESET UINC — — — — R/W-0 R-0 R-0 R-0 R/W-0 R/W
PIC32MX5XX/6XX/7XX REGISTER 23-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (n = 0 THROUGH 31) bit 6 TXABAT: Message Aborted bit(2) 1 = Message was aborted 0 = Message completed successfully bit 5 TXLARB: Message Lost Arbitration bit(3) 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent bit 4 TXERR: Error Detected During Transmission bit(3) 1 = A bus error occured while the message was being sent 0 = A bus error did not occur while the message was being
PIC32MX5XX/6XX/7XX REGISTER 23-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (n = 0 THROUGH 31) Bit Bit Bit Bit Bit Bit Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 31:24 23:16 15:8 7:0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — TXNFULLIE TXHALFIE TXEMPTYIE U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — TXNFULLIF(1
PIC32MX5XX/6XX/7XX REGISTER 23-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (n = 0 THROUGH 31) bit 9 TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) 1 = FIFO is half full 0 = FIFO is > half full TXEN = 0: (FIFO configured as a receive buffer) Unused, reads ‘0’ bit 8 TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit(1) TXEN = 1: (FIFO configured as a transmit buffer) 1 = FIFO is empty 0 = FIFO is not empty, at least 1 message queued to be
PIC32MX5XX/6XX/7XX REGISTER 23-22: CiFIFOUAn: CAN FIFO USER ADDRESS REGISTER ‘n’ (n = 0 THROUGH 31) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-x R-x R-x Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-x R-0(1) R-0(1) CiFIFOUAn<31:24> R-x R-x R-x R-x R-x CiFIFOUAn<23:16> R-x R-x R-x R-x R-x CiFIFOUAn<15:8> R-x R-x R-x R-x R-x CiFIFOUAn<7:0> Legend: R = Readable bit -n = Value at
PIC32MX5XX/6XX/7XX 24.0 ETHERNET CONTROLLER Key features of the Ethernet Controller include: Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 35. “Ethernet Controller” (DS60001155) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX Table 24-1, Table 24-2, Table 24-3 and Table 24-4 show four interfaces and the associated pins that can be used with the Ethernet Controller.
PIC32MX5XX/6XX/7XX 24.
PIC32MX5XX/6XX/7XX REGISTER 24-1: bit 7 ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 (CONTINUED) AUTOFC: Automatic Flow Control bit 1 = Automatic Flow Control is enabled 0 = Automatic Flow Control is disabled Setting this bit will enable automatic Flow Control. If set, the full and empty watermarks are used to automatically enable and disable the Flow Control, respectively. When the number of received buffers BUFCNT (ETHSTAT<16:23>) rises to the full watermark, Flow Control is automatically enabled.
PIC32MX5XX/6XX/7XX REGISTER 24-2: Bit Range ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2 Bit 31/23/15/7 31:24 23:16 15:8 7:0 Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — — — — RXBUFSZ<3:0> RXBUFSZ<6
PIC32MX5XX/6XX/7XX REGISTER 24-3: Bit Range 31:24 23:16 15:8 7:0 ETHTXST: ETHERNET CONTROLLER TX PACKET DESCRIPTOR START ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — TXSTADDR<31:24> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXSTADDR<23:16> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXSTADDR<15:8> R/W-0 R
PIC32MX5XX/6XX/7XX REGISTER 24-5: Bit Range ETHHT0: ETHERNET CONTROLLER HASH TABLE 0 REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 HT<31:24> R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 HT<23:16> 15:8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HT<15:8> 7:0 R/W-0 HT<7:0> L
PIC32MX5XX/6XX/7XX REGISTER 24-7: Bit Range 31:24 ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMM<31:24> R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 31-24 bit 23-16 bit 15-8 bit 7-0 Note 1: 2: R/W-0 R/W-0 R/W-0 W = Writable bit ‘1’ = B
PIC32MX5XX/6XX/7XX REGISTER 24-9: Bit Range 31:24 23:16 15:8 7:0 ETHPMCS: ETHERNET CONTROLLER PATTERN MATCH CHECKSUM REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Note 1: 2: U-0 PMCS<15:8> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMCS<7:0> Legend: R = Rea
PIC32MX5XX/6XX/7XX REGISTER 24-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit Bit 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HTEN MPEN — NOTPM R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R
PIC32MX5XX/6XX/7XX REGISTER 24-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION REGISTER (CONTINUED) bit 7 bit 6 bit 5 bit 4 CRCERREN: CRC Error Collection Enable bit 1 = The received packet CRC must be invalid for the packet to be accepted 0 = Disable CRC Error Collection filtering This bit allows the user to collect all packets that have an invalid CRC.
PIC32MX5XX/6XX/7XX REGISTER 24-12: ETHRXWM: ETHERNET CONTROLLER RECEIVE WATERMARKS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 31:24 23:16 RXFWM<7:0> U-0 15:8 7:0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXEWM<7:0
PIC32MX5XX/6XX/7XX REGISTER 24-13: ETHIEN: ETHERNET CONTROLLER INTERRUPT ENABLE REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 — R/W-0 TXBUSEIE(1) RXBUSEIE(2) R/W-0 R/W-0 RXDONEIE(2) PKTPENDIE
PIC32MX5XX/6XX/7XX REGISTER 24-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 31:24 23:16 15:8 7:0 — TXBUSE RXBUSE — — — EWMARK FWMARK R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W
PIC32MX5XX/6XX/7XX REGISTER 24-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER bit 6 PKTPEND: Packet Pending Interrupt bit 1 = RX packet pending in memory 0 = RX packet is not pending in memory This bit is set when the BUFCNT counter has a value other than ‘0’. It is cleared by either a Reset or by writing the BUFCDEC bit to decrement the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
PIC32MX5XX/6XX/7XX REGISTER 24-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 BUFCNT<7:0> U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ETHBUSY(1) TXBUSY(2) RXBUSY(2)
PIC32MX5XX/6XX/7XX REGISTER 24-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER (CONTINUED) bit 5 RXBUSY: Receive Busy bit(2) 1 = RX logic is receiving data 0 = RX logic is idle This bit indicates that a packet is currently being received. A change in this status bit is not necessarily reflected by the RXDONE interrupt, as RX packets may be aborted or rejected by the RX filter. bit 4-0 Unimplemented: Read as ‘0’ Note 1: 2: This bit will be set when the ON bit (ETHCON1<15>) = 1.
PIC32MX5XX/6XX/7XX REGISTER 24-16: ETHRXOVFLOW: ETHERNET CONTROLLER RECEIVE OVERFLOW STATISTICS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 23:16 15:8 7:0 RXOVFLWCNT<15:8> R/W-0
PIC32MX5XX/6XX/7XX REGISTER 24-17: ETHFRMTXOK: ETHERNET CONTROLLER FRAMES TRANSMITTED OK STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMTXOKCNT<15:8> R/
PIC32MX5XX/6XX/7XX REGISTER 24-18: ETHSCOLFRM: ETHERNET CONTROLLER SINGLE COLLISION FRAMES STATISTICS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 31:24 23:16 15:8 7:0 SCOLFRMCNT<15:8>
PIC32MX5XX/6XX/7XX REGISTER 24-19: ETHMCOLFRM: ETHERNET CONTROLLER MULTIPLE COLLISION FRAMES STATISTICS REGISTER Bit Range 31:24 23:16 15:8 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MCOLFRMCNT<15:8> R/W-0 7:0 Bit 24/16/8/0 Bit 31/23/15/7 R/W-0 R/W
PIC32MX5XX/6XX/7XX REGISTER 24-20: ETHFRMRXOK: ETHERNET CONTROLLER FRAMES RECEIVED OK STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMRXOKCNT<15:8> R/W-0 R/W-0 R/W-0 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 24-21: ETHFCSERR: ETHERNET CONTROLLER FRAME CHECK SEQUENCE ERROR STATISTICS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FCSERRCNT<15:8>
PIC32MX5XX/6XX/7XX REGISTER 24-22: ETHALGNERR: ETHERNET CONTROLLER ALIGNMENT ERRORS STATISTICS REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALGNERRCNT<15:8> R/W-0 7:0 R/W-0 R/W-0 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 24-23: EMAC1CFG1: ETHERNET CONTROLLER MAC CONFIGURATION 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 RESET RFUN RESET TMCS RESET TFUN R/W-1 R/W-0 SOFT RESET SIM RESET — — RESET RMCS U-0
PIC32MX5XX/6XX/7XX REGISTER 24-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 25/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — EXCESS DFR BPNOBK OFF NOBK OFF — — LONGPRE PUREPRE R/W-1 R/W-0 R/W-
PIC32MX5XX/6XX/7XX REGISTER 24-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER bit 6 VLANPAD: VLAN Pad Enable bit(1,2) 1 = The MAC will pad all short frames to 64 bytes and append a valid CRC 0 = The MAC does not perform padding of short frames bit 5 PADENABLE: Pad/CRC Enable bit(1,3) 1 = The MAC will pad all short frames 0 = The frames presented to the MAC have a valid length bit 4 CRCENABLE: CRC Enable1 bit 1 = The MAC will append a CRC to every frame whether padding was required or n
PIC32MX5XX/6XX/7XX REGISTER 24-25: EMAC1IPGT: ETHERNET CONTROLLER MAC BACK-TO-BACK INTERPACKET GAP REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 24-26: EMAC1IPGR: ETHERNET CONTROLLER MAC NON-BACK-TO-BACK INTERPACKET GAP REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 — U-0 NB2BIPKTGP1
PIC32MX5XX/6XX/7XX REGISTER 24-27: EMAC1CLRT: ETHERNET CONTROLLER MAC COLLISION WINDOW/RETRY LIMIT REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U-0 U-0 U-0 U-0 CWINDOW<5:0> — — — —
PIC32MX5XX/6XX/7XX REGISTER 24-28: EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 MACMAXF<15:8>(1) R/W-1 R/W-1 R/W-1 R/W-0 R/W-
PIC32MX5XX/6XX/7XX REGISTER 24-29: EMAC1SUPP: ETHERNET CONTROLLER MAC PHY SUPPORT REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 Bit 27/19/11/3 Bit Bit 26/18/10/2 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 — — — — RESETRMII(1) — — SPEEDRMII(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — —
PIC32MX5XX/6XX/7XX REGISTER 24-30: EMAC1TEST: ETHERNET CONTROLLER MAC TEST REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — TESTBP TESTPAUSE(1)
PIC32MX5XX/6XX/7XX REGISTER 24-31: EMAC1MCFG: ETHERNET CONTROLLER MAC MII MANAGEMENT CONFIGURATION REGISTER Bit Range Bit 31/23/15/7 31:24 23:16 15:8 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 RESETMGMT — — — — — — — U-0 U-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W
PIC32MX5XX/6XX/7XX REGISTER 24-32: EMAC1MCMD: ETHERNET CONTROLLER MAC MII MANAGEMENT COMMAND REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — —
PIC32MX5XX/6XX/7XX REGISTER 24-33: EMAC1MADR: ETHERNET CONTROLLER MAC MII MANAGEMENT ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PHYADDR<4:0> R/
PIC32MX5XX/6XX/7XX REGISTER 24-34: EMAC1MWTD: ETHERNET CONTROLLER MAC MII MANAGEMENT WRITE DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MWTD<15:8> R/W-0 R/W-0
PIC32MX5XX/6XX/7XX REGISTER 24-36: EMAC1MIND: ETHERNET CONTROLLER MAC MII MANAGEMENT INDICATORS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — —
PIC32MX5XX/6XX/7XX REGISTER 24-37: EMAC1SA0: ETHERNET CONTROLLER MAC STATION ADDRESS 0 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — R/W-P R/W-P R/W-P R/W-P — R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P STNADDR6<7:0> R/W-P R/W-P STNAD
PIC32MX5XX/6XX/7XX REGISTER 24-38: EMAC1SA1: ETHERNET CONTROLLER MAC STATION ADDRESS 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P STNADDR4<7:0> R/W-P R/W-P STNA
PIC32MX5XX/6XX/7XX REGISTER 24-39: EMAC1SA2: ETHERNET CONTROLLER MAC STATION ADDRESS 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — R/W-P R/W-P R/W-P R/W-P — R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P STNADDR2<7:0> R/W-P R/W-P STNADDR
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 330 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 25.0 COMPARATOR The Comparator module contains two comparators that can be configured in a variety of ways. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Comparator” (DS60001110) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX 25.
PIC32MX5XX/6XX/7XX REGISTER 25-2: Bit Range 31:24 23:16 15:8 7:0 CMSTAT: COMPARATOR STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 — — R/W-0 U-0 U-0 U-0 U-0 U-0 SIDL — — — — — U-0 U-0 — — U-0 U-0 U-0 U-0 R-0 R-0 — — — — C2OUT C1OUT Legend: R = Read
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 334 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 26.0 COMPARATOR VOLTAGE REFERENCE (CVREF) The CVREF module is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 20.
PIC32MX5XX/6XX/7XX 26.
PIC32MX5XX/6XX/7XX 27.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “PowerSaving Features” (DS60001130) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX The processor will exit, or ‘wake-up’, from Sleep on one of the following events: • On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. • On any form of device Reset • On a WDT time-out If the interrupt priority is lower than or equal to the current priority, the CPU will remain Halted, but the PBCLK will start running and the device will enter into Idle mode. 27.3.
PIC32MX5XX/6XX/7XX 28.0 Note: SPECIAL FEATURES This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Watchdog Timer and Power-up Timer” (DS60001114), Section 24. “Configuration” (DS60001124) and Section 33.
PIC32MX5XX/6XX/7XX REGISTER 28-1: Bit Range DEVCFG0: DEVICE CONFIGURATION WORD 0 Bit 31/23/15/7 31:24 23:16 15:8 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 26/18/10/2 Bit 25/17/9/1 r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P — — CP — — — BWP r-1 r-1 r-1 r-1 R/P R/P R/P R/P r-1 r-1 r-1 r-1 — — — — R/P R/P — — — — R/P R/P R/P R/P PWP<7:4> r-1 r-1 r-1 r-1 R/P r-1 — — — — ICESEL — DEBUG<1:0> Legend: r = Reserved bit P = Programmable bit R = Readable b
PIC32MX5XX/6XX/7XX REGISTER 28-1: bit 3 DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit 1 = PGEC2/PGED2 pair is used 0 = PGEC1/PGED1 pair is used bit 2 Reserved: Write ‘1’ bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled) 11 = Debugger is disabled 10 = Debugger is enabled 01 = Reserved (same as ‘11’ setting) 00 = Reserved (same as ‘11’ setting) 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX REGISTER 28-2: Bit Range 31:24 23:16 15:8 7:0 DEVCFG1: DEVICE CONFIGURATION WORD 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — R/P r-1 r-1 R/P R/P R/P R/P R/P R/P r-1 R/P R/P R/P FWDTEN — — R/P R/P R/P FCKSM<1:0> WDTPS<4:0> — OSCIOFNC R/P r-1 R/P FPBDIV<1:0> r-1 r-1 R/P IESO — FSOSCEN — — POSCMOD<1:0> R/P R/P
PIC32MX5XX/6XX/7XX REGISTER 28-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 bit 11 Reserved: Write ‘1’ bit 10 OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output is disabled 0 = CLKO output signal is active on the OSCO pin; the Primary Oscillator must be disabled or configured for Externa
PIC32MX5XX/6XX/7XX REGISTER 28-3: Bit Range 31:24 23:16 15:8 7:0 DEVCFG2: DEVICE CONFIGURATION WORD 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — r-1 r-1 r-1 r-1 r-1 R/P R/P R/P — — — — — R/P r-1 r-1 r-1 r-1 UPLLEN — — — — r-1 R/P-1 R/P R/P-1 r-1 — FPLLMUL<2:0> FPLLODIV<2:0> R/P R/P R/P UPLLIDIV<2:0> R/P — R/P R/P FPLLIDIV<2:
PIC32MX5XX/6XX/7XX REGISTER 28-3: bit 2-0 DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) FPLLIDIV<2:0>: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX REGISTER 28-4: Bit Range 31:24 DEVCFG3: DEVICE CONFIGURATION WORD 3 Bit 31/23/15/7 Bit 30/22/14/6 R/P R/P FVBUSONIO FUSBIDIO 23:16 15:8 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 r-1 r-1 r-1 R/P R/P R/P — — — FCANIO(1) FETHIO(2) FMIIEN(2) R/P R/P R/P r-1 r-1 r-1 r-1 r-1 — — — — — R/P R/P R/P R/P R/P FSRSSEL<2:0> R/P R/P R/P R/P R/P R/P USERID<15:8> R/P 7:0 R/P R/P R/P R/P USERID<7:0> Lege
PIC32MX5XX/6XX/7XX REGISTER 28-5: Bit Range 31:24 23:16 15:8 7:0 DEVID: DEVICE AND REVISION ID REGISTER Bit 31/23/15/7 Bit 30/22/14/6 R R Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 R R R R R R R (1) R R R R R (1) R R R R R R R VER<3:0> R Bit 24/16/8/0 R (1) (1) R Bit 25/17/9/1 DEVID<27:24> DEVID<23:16> R R R R R R R DEVID<15:8> R DEVID<7:0>(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ =
PIC32MX5XX/6XX/7XX 28.2 Watchdog Timer (WDT) Key features of the WDT module include: This section describes the operation of the WDT and Power-up Timer of the PIC32MX5XX/6XX/7XX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler.
PIC32MX5XX/6XX/7XX REGISTER 28-6: Bit Range 31:24 23:16 15:8 7:0 WDTCON: WATCHDOG TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ON(1,2) — — — — — — — U-0 R-y R-y R-y R-y R-y R/W-0 R/W-0 — SWDTPS<4:0> WDTWINEN WDTCLR Leg
PIC32MX5XX/6XX/7XX 28.3 On-Chip Voltage Regulator All PIC32MX5XX/6XX/7XX devices’ core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX5XX/6XX/7XX family incorporate an on-chip regulator providing the required core logic voltage from VDD. A low-ESR capacitor (such as tantalum) must be connected to the VCAP pin (see Figure 28-2). This helps to maintain the stability of the regulator.
PIC32MX5XX/6XX/7XX REGISTER 28-7: Bit Range 31:24 23:16 15:8 7:0 DDPCON: DEBUG DATA PORT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-1 R/W-0 U-0 R/W-0 — — — — JTAGEN TROEN — TDOEN Leg
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 352 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 29.0 INSTRUCTION SET The PIC32MX5XX/6XX/7XX family instruction set complies with the MIPS32 Release 2 instruction set architecture. The PIC32 device family does not support the following features: • Core Extend instructions • Coprocessor 1 instructions • Coprocessor 2 instructions Note: Refer to “MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set” at www.mips.com for more information. 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 354 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 30.
PIC32MX5XX/6XX/7XX 30.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 30.
PIC32MX5XX/6XX/7XX 30.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC32MX5XX/6XX/7XX 30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC32MX5XX/6XX/7XX 31.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX5XX/6XX/7XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX5XX/6XX/7XX devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC32MX5XX/6XX/7XX 31.1 DC Characteristics TABLE 31-1: OPERATING MIPS VS. VOLTAGE VDD Range (in Volts)(1) Characteristic Max. Frequency Temp. Range (in °C) PIC32MX5XX/6XX/7XX DC5 2.3-3.6V -40°C to +85°C 80 MHz DC5b 2.3-3.6V -40°C to +105°C 80 MHz Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN.
PIC32MX5XX/6XX/7XX TABLE 31-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Conditions Operating Voltage Supply Voltage 2.3 — 3.6 V — DC10 VDD (1) RAM Data Retention Voltage 1.75 — — V — DC12 VDR VDD Start Voltage to Ensure 1.75 — 2.
PIC32MX5XX/6XX/7XX TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Param. No. Typical(3) Max.
PIC32MX5XX/6XX/7XX TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Param. No. Typical(3) Max.
PIC32MX5XX/6XX/7XX TABLE 31-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE)(1) for PIC32MX575/675/695/775/795 Family Devices DC30 4.5 6.
PIC32MX5XX/6XX/7XX TABLE 31-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Parameter No. Typical(2) Max. Units Conditions Idle Current (IIDLE)(1) for PIC32MX534/564/664/764 Family Devices DC30a 1.5 5 DC30c 3.
PIC32MX5XX/6XX/7XX TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) DC CHARACTERISTICS Param. Typical(2) No. Max. Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) DC CHARACTERISTICS Param. Typical(2) No. Max. Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp Characteristics Min. Typical(1) Max. Units DI15 DI16 DI17 DI18 Input Low Voltage I/O Pins: with TTL Buffer with Schmitt Trigger Buffer MCLR(2) OSC1 (XT mode) OSC1 (HS mode) SDAx, SCLx VSS VSS VSS VSS VSS VSS — — — — — — 0.
PIC32MX5XX/6XX/7XX TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. IIL Characteristics Input Leakage Current(3) I/O Ports Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp Min. Typical(1) Max.
PIC32MX5XX/6XX/7XX TABLE 31-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-temp DC CHARACTERISTICS Param.
PIC32MX5XX/6XX/7XX TABLE 31-11: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical(1) Max. Units Conditions — Program Flash Memory(3) D130 EP Cell Endurance 1000 — — E/W D130a EP Cell Endurance 20,000 — — E/W See Note 4 D131 VPR VDD for Read 2.3 — 3.
PIC32MX5XX/6XX/7XX TABLE 31-13: COMPARATOR SPECIFICATIONS Standard Operating Conditions (see Note 3): 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical Max. Units Comments D300 VIOFF Input Offset Voltage — ±7.
PIC32MX5XX/6XX/7XX TABLE 31-14: VOLTAGE REFERENCE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp DC CHARACTERISTICS Param. Symbol No. Characteristics D310 VRES Resolution D311 VRAA Absolute Accuracy (1) D312 TSET Settling Time D313 VIREF Internal Voltage Reference Note 1: Min. Typical Max.
PIC32MX5XX/6XX/7XX 31.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX5XX/6XX/7XX AC characteristics and timing parameters.
PIC32MX5XX/6XX/7XX TABLE 31-17: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Min. Typical(1) Max.
PIC32MX5XX/6XX/7XX TABLE 31-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max. Units OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 3.
PIC32MX5XX/6XX/7XX TABLE 31-20: INTERNAL RC ACCURACY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No. Characteristics Min. Typical Max. Units Conditions -15 — +15 % — LPRC @ 31.25 kHz(1) F21 LPRC Note 1: Change of LPRC frequency as VDD changes.
PIC32MX5XX/6XX/7XX FIGURE 31-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) CPU Starts Fetching Code SY00 (TPU) (Note 1) Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) SY00 (TPU) (Note 1) Note 1: 2: SY10 (TOST) CPU Starts Fetching Code The power-up period will be
PIC32MX5XX/6XX/7XX FIGURE 31-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY) SY02 Reset Sequence CPU Starts Fetching Code TOST (SY10) TABLE 31-22: RESETS TIMING Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX FIGURE 31-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 Tx20 OS60 TMRx Note: Refer to Figure 31-1 for load conditions. TABLE 31-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No.
PIC32MX5XX/6XX/7XX TABLE 31-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Max. Units TB10 TTXH TxCK Synchronous, with High Time prescaler [(12.5 ns or 1 TPB)/N] + 25 ns — ns TB11 TTXL TxCK Synchronous, with Low Time prescaler [(12.
PIC32MX5XX/6XX/7XX FIGURE 31-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 31-1 for load conditions. TABLE 31-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp Characteristics(1) Min. Max. Units Conditions IC10 TCCL ICx Input Low Time [(12.
PIC32MX5XX/6XX/7XX FIGURE 31-9: OCx/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx OCx is tri-stated Note: Refer to Figure 31-1 for load conditions. TABLE 31-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param No.
PIC32MX5XX/6XX/7XX FIGURE 31-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP31 SDIx LSb SP30 MSb In LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX FIGURE 31-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKX (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKX (CKP = 1) SP35 LSb Bit 14 - - - - - -1 MSb SDOX SP30,SP31 SDIX Bit 14 - - - -1 MSb In SP40 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX FIGURE 31-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIX MSb In SP40 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX FIGURE 31-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDI SDIx MSb In SP40 SP51 Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure 31-1 for load conditions. TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.
PIC32MX5XX/6XX/7XX TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No. Symbol Characteristics(1) Min. Typical(2) Max.
PIC32MX5XX/6XX/7XX FIGURE 31-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 31-1 for load conditions. FIGURE 31-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 31-1 for load conditions. 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. IM10 IM11 Min.(1) Max.
PIC32MX5XX/6XX/7XX FIGURE 31-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition Note: Refer to Figure 31-1 for load conditions. FIGURE 31-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 31-1 for load conditions. 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No.
PIC32MX5XX/6XX/7XX FIGURE 31-18: CiTx Pin (output) CAN MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CiRx Pin (input) CA20 TABLE 31-34: CAN MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param No.
PIC32MX5XX/6XX/7XX TABLE 31-35: ETHERNET MODULE SPECIFICATIONS Standard Operating Conditions (see Note 1): 2.9V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No. Characteristic Min. Typical Max.
PIC32MX5XX/6XX/7XX FIGURE 31-21: TRANSMIT SIGNAL TIMING RELATIONSHIPS AT THE MII VIHMIN VILMAX TX Clock VIHMIN ETXD<3:0>, ETEN, ETXERR FIGURE 31-22: VILMAX ET7 RECEIVE SIGNAL TIMING RELATIONSHIPS AT THE MII VIHMIN RX Clock VILMAX VIHMIN ERXD<3:0>, ERXDV, ERXERR VILMAX (Setup) ET10 ET10 (Hold) 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX TABLE 31-36: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions (see Note 5): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp Min. Typical Max. Units Greater of VDD – 0.3 or 2.5 — Lesser of VDD + 0.3 or 3.6 V VSS — VSS + 0.
PIC32MX5XX/6XX/7XX TABLE 31-36: ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param. No. Symbol Characteristics Standard Operating Conditions (see Note 5): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp Min. Typical Max. Units Conditions ADC Accuracy – Measurements with Internal VREF+/VREFAD20d Nr Resolution AD21d INL Integral Nonlinearity > -1 — <1 LSb VINL = AVSS = 0V, AVDD = 2.5V to 3.
PIC32MX5XX/6XX/7XX TABLE 31-37: 10-BIT ADC CONVERSION RATE PARAMETERS Standard Operating Conditions (see Note 3): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp ADC Speed(2) 1 Msps to 400 ksps(1) TAD Minimum 65 ns Sampling RS Time Maximum Minimum 132 ns 500 VDD ADC Channels Configuration 3.0V to 3.6V VREF- VREF+ ANx CHX S&H Up to 400 ksps 200 ns 200 ns 5.0 k ADC 2.5V to 3.
PIC32MX5XX/6XX/7XX TABLE 31-38: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS Standard Operating Conditions (see Note 4): 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics Min. Typical(1) Max.
PIC32MX5XX/6XX/7XX FIGURE 31-23: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP ch0_dischrg ch0_samp eoc AD61 AD60 AD55 TSAMP AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets ADxCON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 17.
PIC32MX5XX/6XX/7XX FIGURE 31-24: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) AD50 ADCLK Instruction Execution Set ADON SAMP ch0_dischrg ch0_samp eoc TSAMP TSAMP AD55 TCONV AD55 CONV ADxIF Buffer(0) Buffer(1) 1 2 3 4 5 6 7 3 4 5 6 8 3 4 1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described in Section 17.
PIC32MX5XX/6XX/7XX FIGURE 31-25: PARALLEL SLAVE PORT TIMING CS PS5 RD PS6 WR PS4 PS7 PMD<7:0> PS1 PS3 PS2 TABLE 31-39: PARALLEL SLAVE PORT REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No. Characteristics(1) Symbol Min. Typical Max.
PIC32MX5XX/6XX/7XX FIGURE 31-26: PARALLEL MASTER PORT READ TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock PM4 Address PMA<13:18> PM6 PMD<7:0> Data Data Address<7:0> Address<7:0> PM2 PM7 PM3 PMRD PM5 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 31-40: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. Symbol No.
PIC32MX5XX/6XX/7XX FIGURE 31-27: PARALLEL MASTER PORT WRITE TIMING DIAGRAM TPB TPB TPB TPB TPB TPB TPB TPB PB Clock Address PMA<13:18> PM2 + PM3 Address<7:0> PMD<7:0> Data PM12 PM13 PMRD PM11 PMWR PM1 PMALL/PMALH PMCS<2:1> TABLE 31-41: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. Symbol No.
PIC32MX5XX/6XX/7XX TABLE 31-42: USB OTG ELECTRICAL SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. Symbol No. Characteristics(1) Min. Typical Max. Units Conditions USB313 VUSB3V3 USB Voltage 3.0 — 3.6 V Voltage on VUSB3V3 must be in this range for proper USB operation USB315 VILUSB Input Low Voltage for USB Buffer — — 0.
PIC32MX5XX/6XX/7XX FIGURE 31-28: EJTAG TIMING CHARACTERISTICS TTCKeye TTCKhigh TTCKlow Trf TCK Trf TMS TDI TTsetup TThold Trf Trf TDO TRST* TTRST*low TTDOout TTDOzstate Defined Undefined Trf TABLE 31-43: EJTAG TIMING REQUIREMENTS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +105°C for V-Temp AC CHARACTERISTICS Param. No. Symbol Description(1) Min. Max.
Note: DC AND AC DEVICE CHARACTERISTICS GRAPHS The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 32-1: VOH – 4x DRIVER PINS FIGURE 32-3: -0.045 0.
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 408 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) PIC32MX575F 512H-80I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 0510017 100-Lead TQFP (14x14x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC32MX5XX/6XX/7XX 33.1 Package Marking Information (Continued) 64-Lead QFN (9x9x0.9 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC32MX575F 512H-80I/MR e3 0510017 121-Lead TFBGA (10x10x1.1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN * Note: DS60001156H-page 410 Example PIC32MX575F 512H-80I/BG e3 0510017 124-Lead VTLA (9x9x0.
PIC32MX5XX/6XX/7XX 33.2 Package Details The following sections give the technical details of the packages.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001156H-page 412 2009-2013 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001156H-page 414 2009-2013 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001156H-page 416 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS60001156H-page 418 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX DS60001156H-page 420 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX DS60001156H-page 422 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX 2009-2013 Microchip Technology Inc.
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PIC32MX5XX/6XX/7XX APPENDIX A: MIGRATING FROM PIC32MX3XX/4XX TO PIC32MX5XX/6XX/7XX DEVICES This appendix provides an overview of considerations for migrating from PIC32MX3XX/4XX devices to the PIC32MX5XX/6XX/7XX family of devices. The code developed for the PIC32MX3XX/4XX devices can be ported to the PIC32MX5XX/6XX/7XX devices after making the appropriate changes outlined below.
PIC32MX5XX/6XX/7XX APPENDIX B: REVISION HISTORY Revision A (August 2009) This is the initial released version of this document. Revision B (November 2009) The revision includes the following global update: Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits. Other major changes are referenced by their respective chapter/section in Table B-1.
PIC32MX5XX/6XX/7XX TABLE B-1: MAJOR SECTION UPDATES (CONTINUED) Section Name 4.0 “Memory Organization” Update Description Updated all register tables to include the Virtual Address and All Resets columns. Updated the title of Figure 4-4 to include the PIC32MX575F256L device. Updated the title of Figure 4-6 to include the PIC32MX695F512L and PIC32MX695F512H devices. Also changed PIC32MX795F512L to PIC32MX795F512H. Updated the title of Table 4-3 to include the PIC32MX695F512H device.
PIC32MX5XX/6XX/7XX Revision C (February 2010) The revision includes the following updates, as described in Table B-2: TABLE B-2: MAJOR SECTION UPDATES Section Name “High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers” Update Description Added the following devices: • PIC32MX675F256H • PIC32MX775F256H • PIC32MX775F512H • PIC32MX675F256L • PIC32MX775F256L • PIC32MX775F512L Added the following pins: • EREFCLK • ECRSDV • AEREFCLK • AECRSDV 1.
PIC32MX5XX/6XX/7XX Revision D (May 2010) The revision includes the following updates, as described in Table B-3: TABLE B-3: MAJOR SECTION UPDATES Section Name “High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers” Update Description Updated the initial Flash memory range to 64K. Updated the initial SRAM memory range to 16K. Added the following devices (see Table 1, Table 2, Table 3 and the Pin Diagrams): • • • • • • • • • • • • 4.
PIC32MX5XX/6XX/7XX TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Section Name 4.
PIC32MX5XX/6XX/7XX TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description 1.0 “Electrical Characteristics” Updated the Typical and Maximum DC Characteristics: Operating Current (IDD) in Table 1-5. Updated the Typical and Maximum DC Characteristics: Idle Current (IIDLE) in Table 1-6. Updated the Typical and Maximum DC Characteristics: Power-Down Current (IPD) in Table 1-7. Added DC Characteristics: Program Memory parameters D130a and D132a in Table 1-11.
PIC32MX5XX/6XX/7XX Revision E (July 2010) Revision F (December 2010) Minor corrections were incorporated throughout the document.
PIC32MX5XX/6XX/7XX TABLE B-4: SECTION UPDATES (CONTINUED) Section Name 4.0 “Memory Organization” (Continued) 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX TABLE B-4: SECTION UPDATES (CONTINUED) Section Name 7.0 “Interrupt Controller” 1.0 “Oscillator Configuration” 1.0 “Output Compare” 1.0 “Ethernet Controller” 1.0 “Comparator Voltage Reference (CVREF)” 1.0 “Special Features” 1.
PIC32MX5XX/6XX/7XX Revision G (May 2011) The revision includes the following global update: • All references to VDDCORE/VCAP have been changed to: VCORE/VCAP • Added references to the new V-Temp temperature range: -40ºC to +105ºC TABLE B-5: This revision also includes minor typographical and formatting changes throughout the data sheet text. Major updates are referenced by their respective section in Table B-5.
PIC32MX5XX/6XX/7XX Revision H (March 2013) This revision includes the following global updates: • Where applicable, control register tables have been added to the document • All references to VCORE were removed • All occurrences of XBGA have been updated to: TFBGA • All occurrences of VUSB have been updated to: VUSB3V3 TABLE B-6: This revision also includes minor typographical and formatting changes throughout the data sheet text.
PIC32MX5XX/6XX/7XX TABLE B-6: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section 32.0 “DC and AC Device Characteristics Graphs” This new chapter was added. Section 33.0 “Packaging Information” Added the 124-lead VTLA package information (see Section 33.1 “Package Marking Information” and Section 33.2 “Package Details”). “Product Identification System” Added the TL definition for VTLA packages. 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 438 2009-2013 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX INDEX A D AC Characteristics ............................................................ 374 10-bit Conversion Rate Parameters.......................... 398 ADC Specifications ................................................... 396 Analog-to-Digital Conversion Requirements............. 399 EJTAG Timing Requirements ................................... 406 Ethernet .................................................................... 394 Internal FRC Accuracy..............................
PIC32MX5XX/6XX/7XX Output Compare................................................................ 209 P Packaging ......................................................................... 409 Details ....................................................................... 411 Marking ..................................................................... 409 Parallel Master Port (PMP) ............................................... 229 PIC32 Family USB Interface Diagram...............................
PIC32MX5XX/6XX/7XX EMAC1SA0 (Ethernet Controller MAC Station Address 0)....................................................................... 327 EMAC1SA1 (Ethernet Controller MAC Station Address 1)....................................................................... 328 EMAC1SA2 (Ethernet Controller MAC Station Address 2)....................................................................... 329 EMAC1SUPP (Ethernet Controller MAC PHY Support) . 320 EMAC1TEST (Ethernet Controller MAC Test)..........
PIC32MX5XX/6XX/7XX SPIx Slave Mode (CKE = 1)...................................... 387 Timer1, 2, 3, 4, 5 External Clock............................... 380 UART Reception ....................................................... 224 UART Transmission (8-bit or 9-bit Data)................... 224 Timing Requirements CLKO and I/O ........................................................... 377 Timing Specifications CAN I/O Requirements .............................................
PIC32MX5XX/6XX/7XX THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC32MX5XX/6XX/7XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 5XX F 512 H T - 80 I / PT - XXX Example: PIC32MX575F256H-80I/PT: General purpose PIC32, 32-bit RISC MCU, 256 KB program memory, 64-pin, Industrial temperature, TQFP package.
PIC32MX5XX/6XX/7XX NOTES: DS60001156H-page 446 2009-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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