Datasheet

 2011-2012 Microchip Technology Inc. Preliminary DS61168E-page 85
PIC32MX1XX/2XX
7.0 INTERRUPT CONTROLLER
PIC32MX1XX/2XX devices generate interrupt requests
in response to interrupt events from peripheral modules.
The interrupt control module exists externally to the CPU
logic and prioritizes the interrupt events before
presenting them to the CPU.
The PIC32MX1XX/2XX interrupt module includes the
following features:
• Up to 64 interrupt sources
• Up to 44 interrupt vectors
• Single and multi-vector mode operations
• Five external interrupts with edge polarity control
• Interrupt proximity timer
• Seven user-selectable priority levels for each
vector
• Four user-selectable subpriority levels within each
priority
• Software can generate any interrupt
• User-configurable interrupt vector table location
• User-configurable interrupt vector spacing
FIGURE 7-1: INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the PIC32MX1XX/2XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupt
Controller” (DS61108) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: On PIC32MX1XX/2XX devices, the
dedicated shadow set is not present.
Interrupt Controller
Interrupt Requests
Vector Number
CPU Core
Priority Level