Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SSOP 28 32-Bit 40 MHz I/O number 21

PIC32MX1XX/2XX

DS61168E-page 42 Preliminary  2011-2012 Microchip Technology Inc.

1110 IPC8

31:16

— — — PMPIP<2:0> PMPIS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000

15:0

— — — I2C1IP<2:0> I2C1IS<1:0> — — —U1IP<2:0>U1IS<1:0>0000

1120 IPC9

31:16

— — — CTMUIP<2:0> CTMUIS<1:0> — — — I2C2IP<2:0> I2C2IS<1:0> 0000

15:0

— — — U2IP<2:0> U2IS<1:0> — — — SPI2IP<2:0> SPI2IS<1:0> 0000

1130 IPC10

31:16

— — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000

15:0

— — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000

TABLE 4-2: INTERRUPT REGISTER MAP (CONTINUED)

Virtual Address

(BF88_#)

Name

(1)

Bit Range

Bits

All

Resets

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 “CLR,

SET and INV Registers” for more information.

2: These bits are not available on PIC32MX1XX devices.

3: This register does not have associated CLR, SET, INV registers.