Datasheet

PIC32MX1XX/2XX

DS61168E-page 204 Preliminary  2011-2012 Microchip Technology Inc.

bit 4 CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated)

1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the

ADC interrupt is generated.

0 = Normal operation, buffer contents will be overwritten by the next conversion sequence

bit 3 Unimplemented: Read as ‘0’

bit 2 ASAM: ADC Sample Auto-Start bit

1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set.

0 = Sampling begins when SAMP bit is set

bit 1 SAMP: ADC Sample Enable bit

(2)

1 = The ADC sample and hold amplifier is sampling

0 = The ADC sample/hold amplifier is holding

When ASAM = 0, writing ‘1’ to this bit starts sampling.

When SSRC = 000, writing ‘0’ to this bit will end sampling and start conversion.

bit 0 DONE: Analog-to-Digital Conversion Status bit

(3)

1 = Analog-to-digital conversion is done

0 = Analog-to-digital conversion is not done or has not started

Clearing this bit will not affect any operation in progress.

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if

ASAM = 1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC

‘0’, this

bit is automatically cleared by hardware to end sampling and start conversion.

3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can

write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation

already in progress. This bit is automatically cleared by hardware at the start of a new conversion.