Datasheet
2011-2012 Microchip Technology Inc. Preliminary DS61168E-page 185
PIC32MX1XX/2XX
bit 4 Unimplemented: Read as ‘0’
bit 3 CS1P: Chip Select 0 Polarity bit
(2)
1 = Active-high (PMCS1)
0 = Active-low (PMCS1)
bit 2 Unimplemented: Read as ‘0’
bit 1 WRSP: Write Strobe Polarity bit
For Slave Modes and Master mode 2 (PMMODE<9:8> = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR
)
For Master mode 1 (PMMODE<9:8> =
11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB
)
bit 0 RDSP: Read Strobe Polarity bit
For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):
1 = Read Strobe active-high (PMRD)
0 = Read Strobe active-low (PMRD
)
For Master mode 1 (PMMODE<9:8> =
11):
1 = Read/write strobe active-high (PMRD/PMWR
)
0 = Read/write strobe active-low (PMRD/PMWR)
REGISTER 19-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.