Datasheet

 2011-2012 Microchip Technology Inc. Preliminary DS61168E-page 181

PIC32MX1XX/2XX

bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit

11 = Reserved; do not use

10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters)

01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters)

00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character)

bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect.

0 = Address Detect mode is disabled

bit 4 RIDLE: Receiver Idle bit (read-only)

1 = Receiver is Idle

0 = Data is being received

bit 3 PERR: Parity Error Status bit (read-only)

1 = Parity error has been detected for the current character

0 = Parity error has not been detected

bit 2 FERR: Framing Error Status bit (read-only)

1 = Framing error has been detected for the current character

0 = Framing error has not been detected

bit 1 OERR: Receive Buffer Overrun Error Status bit.

This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit.

resets the receiver buffer and RSR to empty state.

1 = Receive buffer has overflowed

0 = Receive buffer has not overflowed

bit 0 URXDA: Receive Buffer Data Available bit (read-only)

1 = Receive buffer has data, at least one more character can be read

0 = Receive buffer is empty