Manualshelf

Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SSOP 28 32-Bit 40 MHz I/O number 21
101102103104105106107108109110
2011-2012 Microchip Technology Inc. Preliminary DS61168E-page 107
PIC32MX1XX/2XX
bit 6 CRCAPP: CRC Append Mode bit
(1)
1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer
completes the DMA writes the calculated CRC value to the location given by CHxDSA
0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the
destination
bit 5 CRCTYP: CRC Type Selection bit
1 = The CRC module will calculate an IP header checksum
0 = The CRC module will calculate a LFSR CRC
bit 4-3 Unimplemented: Read as ‘0’
bit 2-0 CRCCH<2:0>: CRC Channel Select bits
111 = CRC is assigned to Channel 7
110 = CRC is assigned to Channel 6
101 = CRC is assigned to Channel 5
100 = CRC is assigned to Channel 4
011 = CRC is assigned to Channel 3
010 = CRC is assigned to Channel 2
001 = CRC is assigned to Channel 1
000 = CRC is assigned to Channel 0
REGISTER 9-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)
Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.